System Memory Design Guidelines (DDR-SDRAM)
R
128
Intel
®
855PM Chipset Platform Design Guide
Pad to First SO-DIMM Pad
Trace Length L3 – First SO-DIMM Pad to Last
SO-DIMM Pad
Max = 1.0”
Figure 74
3
Trace Length L4 – Last SO-DIMM Pad to Parallel
Termination Resistor Pad
Max = 0.80”
Figure 74
Overall routing length from 855PM MCH to last
SO-DIMM Pad– L1+Rs+L2+L3 (required for
DDR333 support)
Min = 0.5”
Max= 4.5”
Series Termination Resistor (Rs)
10
± 5%
Parallel Termination Resistor (Rt)
56
± 5%
Maximum Recommended Motherboard Via
Count Per Signal
6
2,
4
Length Matching Requirements
SDQ[71:0] to SDQS[8:0]
SDQS[8:0] to SCK/SCK#[5:0]
See Section 6.2.1for details
NOTES:
1.
Recommended resistor values and trace lengths may change in a later revision of the design guide.
2.
Power distribution vias from Rt to Vtt are not included in this count.
3.
The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
4.
It is possible to route using 4 vias if trace length L2 is routed on same external layer as SO-DIMM0 and a via is
shared between SO-DIMM1 and parallel termination resistor.
5.
L1 trace length does not include MCH-M package length and should not be used when calculating L1 length.
6.
Implementing a space to trace ratio of 3:1 (e.g. 12-mil space to 4-mil trace) for DQS[8:0] will produce a design
with increased timing margins.
