Platform Design Checklist
R
294
Intel
®
855PM Chipset Platform Design Guide
Intel 855PM MCH – System Memory Interface
Pin Name
System
Pull up/Pull down
Series
Resistor (
Notes
9
See Figure 153 and Section 11.5.3.1 for details.
SRAS#
Pull up to
Vcc1_25[DDR_Vtt]
56
10
Two routing topologies available for these
signals. See Section 6.1.3 for routing
requirements.
SWE#
Pull up to
Vcc1_25[DDR_Vtt]
56
10
Two routing topologies available for these
signals. See Section 6.1.3 for routing
requirements.
Intel 855PM MCH – System Memory Clock Signals
SCK[5:0],
SCK[5:0]#
These differential clock signals can be routed to
any SO-DIMM provided that the BIOS
understands the routing implementation.
Trace width option #2 (inner layer trace width=7
mils) is the recommended implementation for
improved DDR timing margin.
See Section 6.1.4 for routing requirements.
Note that MCH package lengths must be
accounted for when length matching DDR
strobes and clocks. See package length
information in Section 6.2.
If ECC is NOT Supported
:
The 3
rd
differential clock pair routed to each SO-
DIMM for ECC should be left as NC (No
Connect). Intel design guidelines assume non-
ECC memory utilizes only 2 SCK clock pairs.
Intel 855PM MCH – System Memory Power Signals
VCCSM[37:0]
Tie to VccSus2_5
See Section 14.6.4 for VccSus2_5 decoupling
requirement.
NOTE:
Default tolerance for resistors is +/-5% unless otherwise specified.
