System Memory Design Guidelines (DDR-SDRAM)
R
144
Intel
®
855PM Chipset Platform Design Guide
6.1.3.2.
Command Topology 2 Solution
6.1.3.2.1.
Routing Description for Command Topology 2
The command signal group routing starting from Intel 855PM MCH is as follows. The command signal
routing should transition immediately from an external layer to an internal signal layer under the MCH.
Keep to the same internal layer until transitioning back to an external layer at the series resistor Rs. At
this point there is a T in the topology. One leg of the T will route through Rs and either transition back
to the same internal layer or stay external and landing on the appropriate connector pad of SO-DIMM0.
If it was necessary to return to the internal layer from Rs the signal should return to the external layer
immediately prior to landing on the appropriate connector pad of SO-DIMM0. The other leg of the T
will continue on the same internal layer and return to the external layer immediately prior to landing on
the appropriate connector pad of
SO-DIMM1. If possible stay on the external layer and connect to the
parallel termination resistor or if the parallel termination resistor is on the opposite side of the board
from the SO-DIMM1 connector then share the via and route to the parallel termination resistor. If
sharing the via or using the opposite side of the board is not possible, continue on the same internal layer
and route to the external layer immediately prior to the termination resistor.
External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both
sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground referenced to keep the path of the return current continuous. It is recommended that
command signal group be routed on same internal layer.
It is suggested that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
Resistor packs are acceptable for the series and parallel command termination resistors, but command
signals can not be placed within the same R-packs as data, strobe or control signals. The diagrams and
tables below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1.
Figure 82. Command Signal Routing for Topology 2
SO-DIMM1 PAD
SO-DIMM0 PAD
Vtt
L1
L3
Rt
Rs
L2
L4
MCH Pkg Route
MCH
Die
P
Intel 855PM MCH
The command signals should be routed using 1:2 trace to space ratio for signals within the command
group. There should be a minimum of 20 mils of spacing to non-DDR related signals and DDR clock
