Platform Clock Routing Guidelines
R
242
Intel
®
855PM Chipset Platform Design Guide
10.2.6.
USBCLK Clock Group
The driver is the clock synthesizer USB clock output buffer and the receiver is the USB clock input
buffer at the ICH4-M. Note that this clock is asynchronous to any other clock on the board.
Figure 137. USBCLK Group Topology
A
R1
Clock
Driver
ICH4-M
B
Table 69. USBCLK Routing Guidelines
Parameter
Routing Guidelines
Figure
Notes
Signal Group
USBCLK
1
Motherboard Topology
Point-to-Point
Reference Plane
Ground Referenced (Contiguous over entire
length)
Characteristic Trace Impedance (Zo)
55
± 15%
Trace Width
5 mils
Trace to Space Ratio
1:2 (e.g. 5 mils trace 10 mils space)
Group Spacing
Isolation spacing from non-Clock signals =
20 mils minimum
Trace Length – A
Min = 0 inches
Max = 0.50 inches
Figure 137
Trace Length – B
Min = 3.0 inches
Max = 12.0 inches
Figure 137
Series Termination Resistor (R1)
33
± 5%
Figure 137
Skew Requirements
None – USBCLK is asynchronous to any
other clock on the platform
NOTE:
Recommended resistor values and trace lengths may change in a later revision of the design guide.
