FSB Design Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
51
7.
Use the Allegro* “Move ix” (i.e. if vertical routing) command to move the floating section by
the
/2 distance listed in cell B4.
8.
Reconnect the floating segment if needed.
9.
Repeat steps 5 through 8 for the reminder of the traces in the group
Figure 15. Trace Length Equalization Procedures with Allegro*
Move ix -
∆
/2
CUT
∆
=Starting Length – Reference Length
REFERENCE LENGTH
5950
STARTING LENGTH
6012
∆
-62
∆
/2
-31
4.1.4.
Asynchronous Signals
4.1.4.1. Topologies
The following sections describe the topologies and layout recommendations for the Asynchronous Open
Drain and CMOS Signals found on the platform.
All Open Drain signals listed in the following sections below must be pulled-up to V
CCP
(1.05 V). If any
of these Open Drain signals are pulled-up to a voltage higher than V
CCP
, the reliability and power
consumption of the processor may be affected. Therefore, it is very important to follow the
recommended pull-up voltage for these signals.
