Hub Interface
R
180
Intel
®
855PM Chipset Platform Design Guide
Table 47. Hub Interface HIREF/HI_VSWING Generation Circuit Specifications
HI_VSWING Voltage
Specification (V)
1
HIREF Voltage
Specification (V)
1
Recommended Resistor Values for the
HIREF Divider Circuit (Ohm)
1/2 VCC1_8 ± 7%
1/2 VCC1_8 ± 7%
R1 = R2 = (100 – 150)
± 1%
C1 = 0.01 µF
C2 = 0.1 µF
NOTE:
7% tolerance includes static and transient tolerances. HIREF and HI_VSWING must track VCC1_8 and to
this end must be ± 2% relative to the instantaneous value of VCC1_8.
The single HIREF divider should not be located more than 3 inches away from either the MCH or
ICH4-M. If the single HIREF divider is located more than 3 inches away, locally generated hub
interface reference voltage dividers should be used instead. The reference voltage generated by a single
HIREF divider should be bypassed to ground with a 0.1-µF capacitor (C2) and at each component with
a 0.01-µF capacitor (C1) located close to the component HIREF pin. If the reference voltage is
generated locally, the bypass capacitor (0.01 µF) needs to be close to the component HIREF pin.
Figure 95. Hub Interface with Single Reference Voltage Divider Circuit
Intel
ICH4-M
Intel 855PM
MCH
HIREF
HIREF
V
CC
HI=1.8V
R1
C1
R2
C2
C1
HI_VSWING
C1
Figure 96. Hub Interface with Locally Generated Reference Voltage Divider Circuit
HIREF
V
CC
HI=1.8V
Intel
ICH4-M
R1
R2
C1
HI_VSWING
C1
