Intel 855PM, Design Manual

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System Memory Design Guidelines (DDR-SDRAM)
R
150
Intel
®
855PM Chipset Platform Design Guide
Table 31. Clock Signal Group Routing Guidelines
Parameter Routing Guidelines Figure Notes
Signal Group Clock – SCK[5:0], SCK#[5:0] 1
Motherboard Topology Differential Pair Point-to-Point
Reference Plane Ground Referenced
Characteristic Trace Impedance (Zo) 55 ± 15% (single ended)
Trace Width (Option 1)
Inner layers: 4 mils
Outer layers: 5 mils
5, 6
Trace Width (Option 2)
Inner layers: 7 mils
Outer layers: 8 mils
5, 6
Differential Trace Spacing
Inner layers: 4 mils
Outer layers: 5 mils
2
Group Spacing
Isolation spacing from another DDR signal
group = 20 mils minimum
Isolation spacing for non-DDR related
signals = 20 mils minimum
Trace Length L1 – MCH Clock Signal Ball to SO-
DIMM Pad
Min = 0.5”
Max = 5.5”
Figure 85 3, 4
Maximum Recommended Motherboard Via
Count Per Signal
2
Length Matching Requirements
SCK/SCK#[5:0]
The 3 SO-DIMM0 clock pairs are equal in
length plus tolerance and the 3 SO-DIMM1
clock pairs are equal in length plus
tolerance
See Section 6.1.4.1 for details
Clock Pair-to-Pair tolerance ± 25 mils
SCK to SCK# tolerance ± 10 mils
NOTES:
1.
Recommended trace lengths may change in a later revision of the design guide.
2.
Spacing between SCK and SCK# within each differential pair should be implemented as follows with the
following clock trace widths: for microstrips use 4-mil spacing, 4-mil or 7-mil trace width; for striplines use 5-mil
spacing, 5-mil or 8-mil trace width.
3.
The overall maximum and minimum length to the SO-DIMM must comply with DDR signal length matching
requirements.
4.
L1 trace length does not include MCH package length and should not be used when calculating L1 length.
5.
Routing SCK/SCK# to a 7-mil trace width with 4-mil spacing is included as a design enhancement option.
Simulations show improved timing margin resulting from use of a 7-mil clock trace width.
6.
Option 1
OR
Option 2 must be implemented for all SCK/SCK# pairs for a given design. The two options should
not be combined within one design.