FSB Design Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
83
motherboard. A small V
CCP
flood is created on the secondary side under the body of the ITP700FLEX
connector with a 0.1-µF decoupling capacitor. This also provides a convenient connection for the two
54.9-
pull-ups for RESET# and TDO signals as well as the 39.2-
pull-up for the TMS signal.
Notice the very short trace from the 22.6-
series resistors for the RESET# and TDO signals to the
ITP700FLEX pins. See also Section 4.1.5.1 for more details of RESET# signal routing.
The 150-
pull-up resistor for TDI is connected to the V
CCP
(1.05 V) flood on the secondary side close
to processor pin.
The ITP700FLEX TCK pin has a 27.4-
pull-down to ground very close to the ITP700FLEX connector
and also routes to the processor’s TCK pin and loops back with no stub to the FBO pin of the
ITP700FLEX connector.
BCLKp/BCLKn are routed in this example on Layer 3. For more BCLKp/BCLKn routing details, refer
to Figure 28 in Section 4.1.6.
All other signals incorporate a straight forward routing methodology between the ITP700FLEX and
processor pins.
4.3.1.3.
ITP_CLK Routing to ITP700FLEX Connector
A layout example for ITP_CLK/ITP_CLK# routing to an ITP700FLEX connector is shown in Figure
42. The CK-408 clock chip is mounted on the primary side of the motherboard and the differential clock
pair also breaks out on the same side. The differential ITP clock pair routing requires the use of a pair of
33-
± 5% series resistors placed within 0.5 inches of the clock chip output pins followed by a pair of
49.9-
± 1% termination resistors to ground. The ITP_CLK/ITP_CLK# signals route as a differential
pair with a 4-mil trace width on 7-mil spacing from the junction of the 33-
and 49.9-
± 5% resistors
across the internal Layer 6 through an open channel to the ITP700FLEX connector. Serpentining of the
ITP_CLK traces is also performed in order to meet the ± 50 ps length matching requirement between
ITP_CLK and the sum of length L6 of the BCLK[1:0] lines and the additional length L2 of the
BPM#[5:0] signals in Figure 41. The ITP_CLK pair routing then switches back to the primary side layer
through a via near the ITP700FLEX connector.
