I/O Subsystem
R
220
Intel
®
855PM Chipset Platform Design Guide
9.9.4.
Intel 82562ET/EM Disable Guidelines
To disable the Intel 82562ET/EM, the device must be isolated (disabled) prior to reset (RSM_PWROK)
asserting. Using a GPIO, such as GPO28 to be LAN_Enable (enabled high), LAN will default to
enabled on initial power-up and after an AC power loss. This circuit shown below will allow this
behavior. The BIOS controlling the GPIO can disable the LAN micro-controller.
Note:
LAN_RST# needs to be held low for 10 ms after power is stable. It is assumed that RSMRST# logic
will provide this delay. Because GPIO28 will default to high during power up, an AND gate has been
implemented to ensure the required delay for LAN_RST# is met.
Figure 123. Example Intel 82562ET/EM Disable and Power Down Circuitry
LAN_RST#
GPIO[28]
(LAN_Enable)
MMBT2222
VccSus3_3
LAN Device Disable
Ω
10 K
±
5%
Ω
10 K
±
5%
Ω
470
±
5%
RSMRST# Logic
(10 ms delay)
Ω
Rpack
100
±
5%
Test_En
Isol_Tck
Isol_Ti
Isol_Tex
RSMRST#
To ICH5
From ICH5
There are four pins which are used to put the Intel 82562ET/EM controller in different operating states:
Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational/disable features for
this design.
The four control signals shown in the below table should be configured as follows: Test_En should be
pulled-down through a 100-
resistor. The remaining three control signals should each be connected
through 100-
series resistors to the common node “Intel 82562ET/EM _Disable” of the disable circuit.
Table 60. Intel 82562ET/EM Control Signals
Test_En Isol_Tck Isol_Ti Isol_Tex
State
0 0 0 0
Enabled
0
1
1
1
Disabled w/ Clock (low power)
1
1
1
1
Disabled w/out Clock (lowest power)
In addition, if the LAN Connect Interface of the Intel 82801DBM ICH4-M is not used, the VccLAN1_5
and the VccLAN3_3 are still required to be powered during normal operating states. It is acceptable to
power the VccLAN1_5 and VccLAN3_3 power pins by the same voltage source that supplies power to
