Platform Power Requirements
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Intel
®
855PM Chipset Platform Design Guide
93
demand of the processor and future Intel Pentium M/Intel Celeron M family processor, it is strongly
recommended that the VCCA feed resistance from the 1.8 V power supply up to the VCCA shorting
scheme described below be less than
0.1
. Intel recommends that the main VCCA feed be connected to
the processor VCCA0 pin.
Figure 46 illustrates the recommended layout example of the VCCA[3:0] pins feed and decoupling. The
1.8-V flood on Layer 3 from Intel 855PM MCH is via’ed up to the primary side layer with a cluster of
five 1.8-V vias and two GND stitching vias as shown on the left and middle side of Figure 46. On the
primary layer side, a wide flood in a “U-Shape” shorts the four VCCA[3:0] pins of the processor. To
minimize resistance and inductance of the “U-Shaped” VCCA flood shorting the VCCA[3:0] pins, the
flood should be at least 100 mils wide and be spaced at least 25 mils from any switching signals. If
possible, a flood wider than the 100-mil minimum should be implemented and should reference a
ground plane only. Do not reference any switching signals or split planes. The recommended wide flood
on the primary side benefits from low inductance connections to the VCCA[3:0] pins due to the close
proximity of the Layer 2 solid ground plane 4 mils below the primary side 1.8-V flood. (Refer to the
stack-up description in Figure 2.) Decoupling capacitors for pin VCCA3 are placed on the primary side
in the vicinity of the GTLREF circuit (refer to Figure 30). No via is required to connect the VCCA3 side
of the capacitors to the VCCA3 pin. The groundside of the VCCA3 capacitors has a small ground flood
that is shared with the GTLREF circuit and connects to internal ground plane with two vias.
VCCA0 capacitors are also placed on the primary side. No via is needed on the VCCA0 side of the
capacitors that connect to the VCCA0 pin. A small ground flood on the primary side shorts the ground
side of the 1206 form factor 10-
F VCCA0 decoupling capacitor via two GND stitching vias to
minimize interaction with FSB routing. The 0603 form factor 10-nF VCCA0 decoupling capacitor
connects to internal ground planes via a single GND stitching via.
VCCA1 decoupling capacitors are placed on the primary side on the bottom right corner of the
processor socket. No via is required to connect the VCCA1 side of the decoupling capacitors to the
VCCA1 pin. A small, ground plane connects the groundside of the 1206 form factor 10-
F VCCA1
capacitors with a pair of vias to an internal ground plane. The 10-
F decoupling capacitor connects to
internal ground planes via a single GND stitching via.
The decoupling capacitors for VCCA2 are placed on the primary side on the right side of the processor
socket. A small ground flood on the primary side is shared by the GND-side of the two required
decoupling capacitors for VCCA2. Both the 10-nF and 10-
F capacitors are placed in a vertical
orientation on the primary side to avoid interaction with FSB routing and do not require vias on the
VCCA2 side to connect to the VCCA2 pin.
