System Memory Design Guidelines (DDR-SDRAM)
R
136
Intel
®
855PM Chipset Platform Design Guide
6.1.2.1.
Control to Clock Length Matching Requirements
The control signals must be 0.5 inches shorter to 1.0 inches longer than their associated differential
clock pairs.
Length matching equation for SO-DIMM0:
X
1
= SCK/SCK#[2:0]
Y
1
= SCS#[1:0] and SCKE[1:0] = L1of Figure 76 where:
( Y
1
– 1.0” )
X
1
( Y
1
+ 0.5” )
Length matching equation for SO-DIMM1:
X
2
= SCK/SCK#[5:3]
Y
2
= SCS#[3:2] and SCKE[3:2] = L1of Figure 76 where:
( Y
2
– 1.0” )
X
2
( Y
2
+ 0.5” )
For example if the clock length of SCK/SCK#[2:0](X
1
) is 3.5 inches then the length of all control signal
routing to SO-DIMM0 must be between 3.0 inches to 4.5 inches, if SCK/SCK#[5:3](X
2
) is 4.5 inches
then the length of all control signal route to SO-DIMM1 must be between 4.0 inches to 5.5 inches.
Figure 77 depicts the length matching requirements between the control and clock signals.
The MCH package lengths do not need to be taken into account for routing length matching purposes.
