Platform Clock Routing Guidelines
R
236
Intel
®
855PM Chipset Platform Design Guide
10.2.2.
CLK66 Clock Group
The driver is the clock synthesizer 66-MHz clock output buffer and the receiver is the 66-MHz clock
input buffer at the Intel 855PM MCH and the Intel 82801DBM ICH4-M. Note that the goal is to have as
little skew between the clocks within this group as possible.
Figure 131. CLK66 Group Topology
A
R1
Clock
Driver
MCH and
ICH4-M
B
Table 64. CLK66 Group Routing Guidelines
Parameter
Routing Guidelines
Figure
Notes
Signal Group
CLK66
1
Motherboard Topology
Point-to-Point
Reference Plane
Ground Referenced (Contiguous over entire
length)
Characteristic Trace Impedance (Zo)
55
± 15%
Trace Width
4 mils
Trace to Space Ratio
1:5 (e.g. 4 mils trace 20 mils space)
Group Spacing
Isolation spacing from non-Clock signals =
20 mils minimum
Trace Length – A
Min = 0 inches
Max = 0.50 inches
Figure 131
Trace Length – B
Min = 4.0 inches
Max = 8.50 inches
Figure 131
Series Termination Resistor (R1)
33
± 5%
Figure 131
Skew Requirements
Minimal skew (~ 0) between clocks within the
CLK66 group
Clock Driver MCH
X
2
Clock Driver to ICH4-M
X ± 100 mils
2
NOTES:
1.
Recommended resistor values and trace lengths may change in a later revision of the design guide.
2.
If the trace length from clock driver to MCH is X, then the trace length from clock driver to ICH4-M must be length
matched within 100 mils.
