Platform Design Checklist
R
Intel
®
855PM Chipset Platform Design Guide
291
CK-408 Clock – Resistor Recommendations
Pin Name
System
Pull up/Pull down
Series Resistor
(
Notes
9
This signal should be driven by the ICH4-
M’s SLP_S3# signal.
REF
33
If the signal is used, one 33
series
resistor is required for each receiver.
If NOT used, this signal can be left as NC
(No Connect).
See Section 10.2.7 for routing
requirements.
SEL[2:1]
Pull down to GND
1K
SEL[0]
Pull up to Vcc3_3
1K
USB
33
If the signal is used, one 33
series
resistor is required for each receiver.
If NOT used, this signal can be left as NC
(No Connect).
XTAL_IN None
See Notes
Connect to XTAL_OUT through a 14.318
MHz clock. Place crystal within 500 mils of
CK-408.
XTAL_OUT None
See Notes
Connect to XTAL_IN through a 14.318
MHz clock. Place crystal within 500 mils of
CK-408.
CK-408 Clock – Power Signals
VDD[7:0], VDDA
Tie to Vcc3_3
See Notes
Also see Section 14.5.2 for decoupling
requirement.
CK-408 Clock – GND Signals
VSS[5:0]
Tie to GND
VSSA
Tie to GND
VSSIREF
Tie to GND
NOTE:
Default tolerance for resistors is +/-5% unless otherwise specified.
