Platform Power Requirements
R
Intel
®
855PM Chipset Platform Design Guide
115
Placement and layout of the ten, 0.1-µF capacitors should be strictly adhered to in order to minimize the
effective loop inductance of these capacitors. All the capacitors should be placed within 45 mils (center-
to-center) of the V
CCP
pin rows. Ground vias for the 0.1-µF capacitors should also be placed within 45
mils of the capacitor pads and shorted with a 25-mil wide trace to the ground via.
In Figure 65, the secondary side shows one of the 150-
F POSCAPs being placed next to the processor
socket close to the DATA pins. Notice that the ground pin connection of the POSCAP is extended
towards the V
CCP
pad of the capacitor with two ground vias placed under the body of the POSCAP. This
is done in order to minimize the inductance of the POSCAP connection by minimizing the loop area of
current flow.
Figure 65 also shows that a connection on the secondary side to the Legacy side V
CCP
pins of the
processor pin-map is not possible because it is blocked by the secondary side V
CC-CORE
flood that
connects the south side 0805 capacitors with the twenty-four V
CC-CORE
pins on the south side of the
processor pin-map (see secondary side of Figure 60 in Section 5.9.3). Thus, the primary side of Figure
65 illustrates a V
CCP
flood shape that shorts the DATA, ADDR, and Legacy V
CCP
pins of the processor
pin-map. The very specific arrangement of the V
CCP
/GND vias illustrated on the primary side of Figure
65 should be strictly followed to guarantee that each V
CCP
BGA ball of the processor pin-map connects
to the V
CCP
shape flood on the primary side. To guarantee robust connection to the ground balls around
the V
CCP
pins, 25-mil wide dog bones should be used while the V
CCP
BGA balls of the processor socket
are advised to use the wide V
CCP
flood in between the Vss dog bones as illustrated on the primary side of
Figure 65.
A V
CCP
flood “channel” should pass through the processor pin field on the bottom right side of the
processor socket to continue the V
CCP
feed to the ITP700FLEX debug port. A V
CCP
flood “channel” to
the ICH4-M is provided from the main V
CCP
flood plane of the MCH and circumvents the 1.5-V and
1.8-V plane floods to the MCH by routing around the AGP bus signal quadrant (not shown in figures).
Refer to Figure 65 for more details.
