AGP Port Design Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
175
Table 42. AGP Pull-Up/Pull-Down Requirements and Straps
Signal
AGP 2.0 Signal
Pull-Up/Pull-Down
Requirements
Intel 855PM
MCH Integrated
Pull-Up/Pull-Down
State During
RSTIN# Assertion
Notes
DEVSEL#
Pull-Up
4.5 k Pull-Up
FRAME#
Pull-Up
4.5 k Pull-Up
GNT#
4.5 k Pull-Up
Pull-Up (Strap)
6
INTA#
Pull-Up
3,
5
INTB#
Pull-Up
3,
5
IRDY#
Pull-Up
4.5 k Pull-Up
PERR#
Pull-Up
2
PIPE#
Pull-Up
4.5 k Pull-Up
RBF#
Pull-Up
4.5 k Pull-Up
Pull-Up (Strap)
6
REQ#
4.5 k Pull-Up
1
SERR#
Pull-Up
2
ST[2:0]
4.5 k Pull-Up
Pull-Up (Strap)
4, 6
STOP#
Pull-Up
4.5 k Pull-Up
TRDY#
Pull-Up
4.5 k Pull-Up
WBF#
4.5 k Pull-Up
Pull-Up (Strap)
6
AD_STB[1:0]
Pull-Up
4.5 k Pull-Up
AD_STB[1:0]#
Pull-Down
4.5 k Pull-Down
SB_STB
Pull-Up
4.5 k Pull-Up
SB_STB#
Pull-Down
4.5 k Pull-Down
SBA[7:0]
4.5 k Pull-Up
Pull-Up (Strap)
1, 6
NOTES:
1.
The Intel 855PM MCH has integrated pull-ups to ensure that these signal do not float when there is no add-in
card in the connector.
2.
The Intel 855PM MCH does not implement the PERR# and SERR# signals. Pull-ups on the motherboard are
required for AGP graphics controllers that implement these signals.
3.
The AGP graphics controller’s INTA# and INTB# signals must but routed to the system PCI interrupt request
handler where the pull-up requirement should be met. For Intel 855PM chipset-based systems, they can be
routed to the ICH4-M’s PIRQ signals that are open drain and require pull-ups on the motherboard.
4.
ST[1:0] provide the strapping options for 100-MHz FSB operation and DDR memory, respectively.
5.
INTA# and INTB# should be pulled to 3.3 V, not VDDQ.
6.
Refer to the
Intel
®
855PM Memory Controller Hub (MCH) DDR 200/266 MHz
Datasheet
for more details on
straps.
The pull-up/pull-down resistor value requirements are shown in Table 43.
Table 43. AGP 2.0 Pull-up Resistor Values
Rmin Rmax
4 k
16
k
The recommended AGP pull-up/pull-down resistor value is 8.2 k
.
