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14
Intel
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855PM Chipset Platform Design Guide
Figure 148. Processor GTLREF Voltage Divider Network .................................................... 282
Figure 149. Routing Illustration for INIT# ............................................................................... 282
Figure 150. Voltage Translation Circuit.................................................................................. 283
Figure 151. Routing Illustration for PROCHOT#.................................................................... 283
Figure 152. Clock Power Down Implementation.................................................................... 292
Figure 153. Reference Voltage Level for SMVREF[1:0] ........................................................ 295
Figure 154. Intel 855PM MCH HSWNG[1:0] Reference Voltage Generation Circuit ........... 299
Figure 155. Intel 855PM MCH HVREF[4:0] Generation Circuit............................................. 299
Figure 156. AGPREF Implementation (On Intel CRB)........................................................... 305
Figure 157. Hub Interface with Signal Reference Voltage Divider Circuit ............................. 316
Figure 158. Hub Interface with Locally Generated Reference Voltage Divider Circuit.......... 316
Figure 159 External Circuitry for the RTC.............................................................................. 318
Figure 160. USBPWR_CONN[E:A] Design Recommendation.............................................. 324
Figure 161. LAN_RST# Design Recommendation (On Intel CRB) ....................................... 327
