FSB Design Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
61
Figure 25. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector
Intel
Pentium M
processor
L1
Intel
855PM
MCH
For a system that implements an ITP700FLEX debug port a more elaborate topology is required in order
to guarantee proper signal quality at both the processor signal pad and the ITP700FLEX input receiver.
In this case the topology illustrated in Figure 26 should be implemented. The CPURST# signal from the
MCH should fork out (do not route one trace from MCH pin and then T-split) towards the processor’s
RESET# pin as well as towards the Rtt and Rs resistive termination network placed next to the
ITP700FLEX debug port connector. Rtt (54.9
± 1%) pulls-up to the V
CCP
voltage and is placed at the
end of the L2 line that is limited to a 12-inch maximum length. Rs (22.6
± 1%) should be placed right
next to Rtt to minimize the routing between them in the vicinity of the ITP700FLEX connector to limit
the L3 length to less than 0.5 inches. ITP700FLEX operation requires the matching of L2 + L3 - L1
length to the length of the BPM[4:0]# signals length within ± 50 ps. Refer to Section 4.3.1 for more
details on ITP700FLEX signal routing and Section 4.1.1.4 for more details on signal propagation time to
distance correlation. See Table 15 for routing length summary and termination resistor values.
Currently 1% tolerance resistors are recommended for Rs and Rtt. The use of 5% tolerant resistors for
these resistors and whether it could provide adequate signal quality performance is under investigation.
Figure 26. Processor RESET# Signal Routing Topology With ITP700FLEX Connector
Intel
Pentium M
processor
L2
L3
Rs
L1
ITPFLEX
CONNECTOR
Intel 855PM
MCH
Rtt
VCCP
RESET#
CPURESET#
RESET#
