I/O Subsystem
R
Intel
®
855PM Chipset Platform Design Guide
195
traces as much as practical. It is preferable to change layers to avoid crossing a plane split. Refer
to Section 9.4.2.
8.
Separate signal traces into similar categories and route similar signal traces together (such as
routing differential pairs together).
9.
Keep USB 2.0 USB signals clear of the core logic set. High current transients are produced during
internal state transitions and can be very difficult to filter out.
10.
Follow the 20*h thumb rule by keeping traces at least 20*(height above the plane) away from the
edge of the plane (VCC or GND, depending on the plane the trace is over). For the suggested
stack-up the height above the plane is 4.5 mils. This calculates to a 90-mil spacing requirement
from the edge of the plane. This helps prevent the coupling of the signal onto adjacent wires and
also helps prevent free radiation of the signal from the edge of the PCB.
9.4.1.2.
USB 2.0 Trace Separation
Use the following separation guidelines.
1.
Maintain parallelism between USB differential signals with the trace spacing needed to achieve
90-
differential impedance. Deviations will normally occur due to package breakout and routing
to connector pins. Just ensure the amount and length of the deviations are kept to the minimum
possible.
2.
Use an impedance calculator to determine the trace width and spacing required for the specific
board stack-up being used. 4-mil traces with 4.5-mil spacing results in approximately 90-
differential trace impedance.
3.
Minimize the length of high-speed clock and periodic signal traces that run parallel to high-speed
USB signal lines, to minimize crosstalk. Based on EMI testing experience, the minimum
suggested spacing to clock signals is 50 mils.
4.
Based on simulation data, use 20-mil minimum spacing between high-speed USB signal pairs and
other signal traces for optimal signal quality. This helps to prevent crosstalk.
Figure 105. Recommended USB Trace Spacing
DP1
DP2
DM1
DM2
Low-speed
non periodic
signal
Clock/High-
speed
periodic signal
20
20
4
4.5
4
4
4.5
4
50
Distance in mils
9.4.1.3. USBRBIAS
Connection
The USBRBIAS pin and the USBRBIAS# pin can be shorted and routed 5 on 5 to one end of a 22.6
±1% resistor to ground. Place the resistor within 500 mils of the Intel 82801DBM ICH4-M and avoid
routing next to clock pins.
