Platform Power Requirements
R
Intel
®
855PM Chipset Platform Design Guide
123
Figure 71 further illustrates a “Zoom In View” of the secondary side layout that was shown on the
bottom left side of Figure 70. Notice the specific locations of the 0805, 2.2-µF mid frequency capacitor
and the 0603 form factor 10 nF, 15 nF, 22 nF, 47 nF, and 220 nF high frequency decoupling capacitors.
The 0603 capacitors’ V
CC-MCH
side pads are placed within 45 mils of their respective row of V
CC-MCH
vias. All these capacitors are shorted with the V
CC-MCH
flood on the secondary side plane to the V
CC-MCH
vias of the pin field and the two extra vias that were added to effectively stitch the primary side, Layer 5,
Layer 6, and the secondary side V
CC-MCH
floods to the decoupling capacitors. The groundside of the
0603 form factor 10 nF, 15 nF, 22 nF, 47 nF, and 220 nF capacitors connect to a ground ring on the
secondary side and a stitching ground via is placed within 45 mils of the ground pad of the capacitor.
On the top left corner of Figure 71 four pairs of the V
CC-MCH
and ground vias connect the two small V
CC-
MCH
and ground floods for the two 150-µF bulk decoupling POSCAPs to internal layers. The V
CC-MCH
vias are offset 25 x 25 mils in the X and Y directions from the ground vias. This cluster of vias is placed
symmetrically under the middle of the body of the POSCAPs.
Figure 71. V
CC-MCH
Secondary Layer Decoupling Capacitor Placement (Zoom in View)
1.05v
1.5v
1.8v
Secondary
Side
2.5v
0603
220nF
0603
22nF
0603
47nF
25mil
25mil
0805
2.2
µ
F
1.2v
0603
10nF
0603
15nF
45mil
45mil
Extra Via
Extra Via
2x150
µ
F
