Platform Design Checklist
R
296
Intel
®
855PM Chipset Platform Design Guide
14.6.1.2.
DDR SO-DIMM Interface
DDR SO-DIMM Interface
Pin Name
System
Pull up/Pull down
Series
Resistor
Notes
9
DDR SO-DIMM – ECC Related Signals
CB[7:0]
See Notes
These signals are ECC related.
If ECC Is Supported
:
These signals need to be routed to MCH. See
SDQ[71:64] in Section 14.6.1.1.
If ECC Is NOT Supported:
These signals can be left as NC (No Connect).
CKx, CKx#
CKy, CKy#
See Notes
These signals are ECC related. CKx/CKx# and
CKy/CKy# are the 3
rd
differential clock signal
used to support ECC memory devices on a
SO-DIMM module.
If ECC Is Supported:
:
These signals need to be routed to MCH. See
SCK[5:0], SCK[5:0]# in Section 14.6.1.1.
If ECC Is NOT Supported:
These signals should be left as NC (No
Connect).
DQS[8] See
Notes
This signal is ECC related.
If ECC Is Supported:
This signal needs to be routed to MCH. See
DQS[8] in Section 14.6.1.1.
If ECC Is NOT Supported:
These signals can be left as NC (No Connect).
DDR SO-DIMM – Reference Voltage Signals
VREF[2:1] See
Notes
In S3, VREF[2:1] are powered ON in Intel
CRB.
Reference voltage = (VccSus2_5 ± 8%) / 2 ±
4%. Note that a buffer is used to provide the
necessary current and reference voltage to
VREF. A simple voltage divider may not be
able to provide the necessary tolerance for
these pins.
See Section 11.5.6 for details.
DDR SO-DIMM Interface-- Power Signals
VDD[33:1]
Tie to VccSus2_5
Power must be supplied during S3.
VDDSPD
Tie to Vcc3_3
DDR SO-DIMM Interface—GND Signals
DM[8:0]
Tie to GND
VSS[31:1]
Tie to GND
DDR SO-DIMM Interface—No Connect Signals
