Platform Clock Routing Guidelines
R
240
Intel
®
855PM Chipset Platform Design Guide
Figure 135. PCICLK Group to PCI Device Down Topology
A
R1
Clock
Driver
PCI Device
B
Table 67. PCICLK Group Routing Guidelines
Parameter
Routing Guidelines
Figure
Notes
Signal Group
PCICLK
1
Motherboard Topology
Point-to-Point
Reference Plane
Ground Referenced (Contiguous over entire
length)
Characteristic Trace Impedance (Zo)
55
±15%
Trace Width
5 mils
Trace to Space Ratio
1:4 (e.g. 5 mils trace 20 mils space)
Group Spacing
Isolation spacing from non-Clock signals =
20 mils minimum
Trace Length – A
Must be exactly trace length matched to
CLK33 Trace A
Figure 135
Trace Length – B
Must be exactly trace length matched to
CLK33 Trace B
Figure 135
Series Termination Resistor (R1)
33
± 5%
Figure 135
Skew Requirements
Maximum of ± 1 ns of skew between clocks
within the PCICLK group and a maximum of
± 1 ns of skew between the clocks of this
group and those of CLK33
NOTE:
Recommended resistor values and trace lengths may change in a later revision of the design guide.
