Platform Power Requirements
R
92
Intel
®
855PM Chipset Platform Design Guide
from the bulk decoupling capacitor via on the secondary side layer also routes through Layer 3 as a
separate branch to the 1.8-V flood that shorts the MCH VCCGA and VCCHA pins. The Hub Interface
1.8-V power delivery pin vias do not connect to the Layer 3 branch of the flood that feeds the VCCGA
and VSSGA pins. The flood continues to the processor’s VCCA[3:0] pins (1.8 V) on Layer 3, routing
between the common clock and source synchronous address signal routing corridor as explained in
Section 4.1.3.4, Figure 11, Figure 12, and Figure 13. The right side of Figure 45 illustrates that the
VCCGA pin is connected with a small flood on the secondary side to a 10-nF 0603 form factor capacitor
while the VCCHA pin with anther flood connects to a 1206 form factor 10-µF capacitor. Each of the
capacitors connect through a via to a robust, wide 1.8 V flood of Layer 3 shown on the left side of
Figure 45. The Layer 1 dog bone connection (not shown in Figure 45) should have a width of 25 mils
for each of the VCCGA and VCCHA pins.
Figure 45. Intel 855PM MCH 1.8 V V
CCGA
and V
CCHA
Recommended Power Delivery
SECONDARY SIDE
LAYER 3
To Pentium M
VCCA
VCCGA
VCCHA
HI 1.8V
VCCGA
VCCHA
DO NOT SHORT
SECONDARY SIDE
LAYER 3
To Pentium M
VCCA
VCCGA
VCCHA
HI 1.8V
VCCGA
VCCHA
DO NOT SHORT
5.2.2.
Intel 855PM MCH PLL Voltage Supply Power Sequencing
See Section 11.4.2 for more details on the platform power sequencing requirements for the 1.8-V supply
to the processor and Intel 855PM MCH’s PLLs.
5.3.
Processor Phase Lock Loop Power Delivery Design
Guidelines
5.3.1.
Processor PLL Power Delivery
V
CCA
[3:0] is a power source required by the PLL clock generators on the processor silicon. Since these
PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to
the system: it degrades external I/O timings as well as internal core timings (i.e. maximum frequency).
Traditionally this supply is low-pass filtered to prevent any performance degradation. The processor has
an internal PLL super filter for the 1.8-V supply to the VCCA [3:0] pins that dispenses with the need for
any external low-pass filtering. However, one 0603 form factor 10-nF and one 1206 form factor 10-
F
decoupling capacitor should be placed as close as possible to each of the four VCCA pins (i.e. a pair of
capacitors consisting of one 10-nF and one 10-
F should be used for each VCCA pin). VCCA power
delivery should meet the 1.8 V ± 5% tolerance at the VCCA pins. As a result, to meet the current
