Platform Power Delivery Guidelines
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Intel
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855PM Chipset Platform Design Guide
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rows of memory are powered off, the VTT termination voltage can be removed. During entry into
suspend and during suspend, VTT must not glitch.
The voltage supplied to VREF (see Notes in 11.5.6), and SMRCOMP can be removed once all rows of
memory are powered off and SCKE must not glitch during entry into suspend and during suspend.
Consult
JEDEC Standard, JESD79, Double Data Rate (DDR) SDRAM Specification
for more details.
11.5.6.2.
VTT Rail Power Up Sequencing During Resume
During resume from the S3 state, the reverse sequencing of the power rails and control signals must
happen to ensure a smooth exit from suspend. The VTT termination voltage must be supplied and steady
for a minimum of 10 ms before the system begins exit from suspend. VTT must not glitch during
resume.
VREF (see NOTES in 11.5.6)), and SMRCOMP also need to be supplied and valid before the assertion
of the SCKE signals. These reference voltages and resistive compensation are necessary in order for the
Intel 855PM MCH and the memory devices to recognize the valid assertion of SCKE to a logic ‘1’.
SCKE must not glitch during resume and must rise monotonically.
VTT and VREF to the SO-DIMMs and SMVREF and SMRCOMP to the MCH must all be up and
stable for a minimum of 10 ms before the deassertion of PCIRST#.
Consult
JEDEC Standard, JESD79, Double Data Rate (DDR) SDRAM Specification
for more details.
11.6.
Clock Driver Power Delivery Guidelines
Special care must be taken to provide a quiet VDDA supply to the Ref VDD, VDDA, and the 48 MHz
VDD. These VDDA signals are especially sensitive to switching noise induced by the other VDDs on
the cock chip. They are also sensitive to switching noise generated elsewhere in the system such as the
CPU VRM. The CLC pi-filter should be designed to provide the best reasonable isolation. It is
recommended that a solid ground plane be underneath the clock chip on Layer 2 (assuming top trace is
Layer 1). Intel also recommends that a ground flood be placed directly under the clock chip to provide a
low impedance connection for the VSS pins.
For ALL power connections to planes, decoupling capacitors and vias, the MAXIMUM trace width
allowable and shortest possible lengths should be used to ensure lowest possible inductance. The
decoupling capacitors should be connected as shown in the illustration taking care to connect the VDD
pins directly to the VDD side of the capacitors. However, the VSS pins should not be connected directly
to the VSS side of the capacitors. Instead they should be connected to the ground flood under the part
that is via’ed to the ground plane. This is done to avoid VDD glitches propagating out, getting coupled
through the decoupling capacitors to the VSS pins. This method has been shown to provide the best
clock performance.
The ground flood should be via’ed through to the ground plane with no less than 12-16 vias under the
part. It should be well connected. For all power connections, heavy duty and/or dual vias should be
used. It is imperative that the standard signal vias and small traces not be used for connecting
decoupling capacitors and ground floods to the power and ground planes. VDDA should be generated
by using a CLC pi-filter. This VDDA should be connected to the VDD side of the three capacitors that
require it using a hefty trace on the top layer. This trace should be routed from the CLC pi-filter using a
star topology.
