Platform Power Delivery Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
253
11.4.2.
Intel 855PM MCH Power Sequencing Requirements
No Intel 855PM MCH power sequencing requirements exist for the system incorporating the Intel
855PM chipset. All MCH power rails should be stable before de-asserting reset, but the power rails can
be brought up in any order desired. Good design practice would have all MCH power rails come up as
close in time as practical, with the core voltage (1.2 V) coming up first.
Although no power sequencing requirements between any of the MCH’s rails exist, there are timing
requirements that must be met with respect to other control signals that indicate the status of platform
power rails. The 1.8-V supply rail that powers the Hub Interface of the MCH also powers the isolated,
analog supply pins for the PLLs on the processor (VCCA[3:0]) and MCH (VCCGA and VCCHA). The
1.8-V supply to the processor must be stable for a minimum of 4
s
before
the ICH4-M’s
CPUPWRGOOD signal can be asserted to the processor’s PWRGOOD input. Similarly, the RSTIN#
input of the MCH must be asserted by the Intel 82801DBM ICH4-M’s PCIRST# signal for a minimum
of 4
s
after
the 1.8-V supply is stable.
11.4.3.
DDR Power Sequencing Requirements
No DDR-SDRAM power sequencing requirements are specified during power up or power down if the
following criteria are met:
VDD and VDDQ are driven from a single power converter output
VTT is limited to 1.44 V (reflecting VDDQ(max)/2 + 50 mV VREF var 40 mV VTT
variation)
VREF tracks VDDQ/2
A minimum resistance of 42
(22
series re 22
parallel resistor ± 5% tolerance)
limits the input current from the VTT supply into any pin
If the above criteria cannot be met by the system design, then the following Table 73 must be adhered to
during power up.
Table 73. DDR Power-Up Initialization Sequence
Voltage Description
Sequencing
Voltage Relationship to Avoid Latch-up
VDDQ
After or with VDD
< VDD + 0.3 V
VTT
After or with VDDQ
< VDDQ + 0.3 V
VREF
After or with VDDQ
< VDQ + 0.3 V
