Platform Power Requirements
R
100
Intel
®
855PM Chipset Platform Design Guide
5.7. Voltage
Regulator
Topology
In a single-phase topology, the duty cycle of the Control (top) MOSFET is roughly the ratio of the
output voltage and the input voltage. Due to the small ratio between V
CC-CORE
and V
DC
, the duty cycle of
the Control MOSFET is very small. The main power loss in the Control MOSFET is therefore due to the
transition or switching loss as it switches on and off. To minimize the transition loss in the Control
MOSFET, its transition time must be minimized. This is usually accomplished with the use of a small-
size MOSFET. Or similarly, the duty cycle of the Synchronous MOSFET is very large; hence, to
minimize the DC loss of the Synchronous MOSFET, its R
DS-ON
must be small. This is usually
accomplished with the use of a large-size MOSFET or several small-size MOSFETs connected in
parallel, but this solution usually leads to shoot-through current as it is quite difficult to minimize the
effect of the Gate-Glitch phenomenon in the Synchronous MOSFET due to C
GD
charge coupling effect.
It is, therefore, necessary to go to multi-phase topology. In a multi-phase topology, the output load
current is sourced from multiple sources or output stages. The term multi-phase implies that the phases
or stages are out of phase with respect to each other. For example, in a dual-phase topology, the stages
are exactly 180
output of phase.
Refer to Figure 51 for a block diagram for a dual-phase topology.
Figure 51. Voltage Regulator Multi-Phase Topology Example
CO2
L
DRIVER
STAGE
V
DC
R
S
CO1
L
DRIVER
STAGE
V
DC
R
S
IMVP-
R
e
g
ul
at
o
r
C
BULK
V
CC
CO2
L
DRIVER
STAGE
V
DC
R
S
CO1
L
DRIVER
STAGE
V
DC
R
S
Voltage
Regulator
C
BULK
V
CC
5.8.
Voltage Regulator Design Recommendations
When laying out the processor power delivery circuit using a traditional Buck Voltage Regulator on a
printed circuit board, the following checklist should be followed.
