System Memory Design Guidelines (DDR-SDRAM)
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Intel
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855PM Chipset Platform Design Guide
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6.1.3.
Command Signals – SMA[12:0], SBS[1:0], SRAS#, SCAS#,
SWE#
The Intel 855PM MCH command signals, SMA[12:0], SBS[1:0], SRAS#, SCAS#, and SWE# are
common clocked signals. They are “clocked” into the DDR-SDRAMs using the clock signals
SCK/SCK#[5:0]. The MCH drives the command and clock signals together, with the clocks crossing in
the valid command window. There are two supported topologies for the command signal group. Section
6.1.3 is divided into two subsections; Topology 1 and Topology 2. Topology 1 is a daisy chain topology.
Topology 2 implements a T routing topology. Both topologies place a series resistor between the two
SO-DIMMs to damp SO-DIMM-to-SO-DIMM resonance. Topology 2 is the topology that best allows
for placement of the SO-DIMMs back to back in the butterfly configuration, thus minimizing the SO-
DIMM footprint area.
6.1.3.1.
Command Topology 1 Solution
6.1.3.1.1.
Routing Description for Command Topology 1
The command signal group routing starting from Intel 855PM MCH is as follows. The command signal
routing should transition immediately from an external layer to an internal signal layer under the MCH.
Keep to the same internal layer until transitioning back to an external layer immediately prior to
connecting the SO-DIMM0 connector pad. At the via transition for SO-DIMM0, continue the signal
route on the same internal layer to the series termination resistor (Rs), collocated to SO-DIMM1. At this
resistor the signal should transition to an external layer immediately prior to the pad of Rs. After the
series resistor, Rs, continue the signal route on the external layer landing on the appropriate connector
pad
of SO-DIMM1, or if necessary return to the same internal layer and return to external layer
immediately prior to the connector pad of SO-DIMM1. After SO-DIMM1, transition to the same
internal layer or stay on the external layer and route the signal to Rt.
It is suggested that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
Resistor packs are acceptable for the series and parallel command termination resistors but command
signals can’t be placed within the same R-packs as data, strobe, or control signals. The diagrams and
tables below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1. Collocating the series resistor, Rs, and SO-
DIMM1 allows for the elimination of one via from the signal route.
Figure 79. Command Signal Routing for Topology 1
R s
SO-DIMM1 PAD
SO-DIMM0 PAD
V tt
L1
L3
L2
R t
L4
MCH Pkg Route
MCH
Die
P
Intel 855PM MCH
R s
SO-DIMM1 PAD
SO-DIMM0 PAD
V tt
L1
L3
L2
R t
L4
MCH Pkg Route
MCH
Die
P
Intel 855PM MCH
