Platform Clock Routing Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
235
MCH (L1 + L2 + L4) = MCH (L1’ + L2’ + L4’) ± 10 mils
10.2.1.2.
BCLK General Routing Guidelines
Below is the general guidelines for routing the BCLK:
1.
When routing the 100-MHz differential clocks, do not split up the two halves of a differential
clock pair between layers and route to all agents on the same physical routing layer referenced to
ground.
2.
If a layer transition is required, make sure that the skew induced by the vias used to transition
between routing layers is compensated in the traces to other agents.
3.
Do not place vias between adjacent complementary clock traces and avoid differential vias. Vias
placed in one half of a differential pair must be matched by a via in the other half. Differential vias
can be placed within length L1, between clock driver and Rs, if needed to shorten length L1.
10.2.1.3. EMI
constraints
Clocks are a significant contributor to EMI and should be treated with care. The following
recommendations can aid in EMI reduction:
1.
Maintain uniform spacing between the two halves of differential clocks.
2.
Route clocks on physical layer adjacent to the VSS reference plane only.
Figure 130. Clock Skew as Measured from Agent-to-Agent
