FSB Design Guidelines
R
58
Intel
®
855PM Chipset Platform Design Guide
4.1.4.1.6.
Topology 2C: CMOS Signals Driven by Intel 82801DBM ICH4-M – LINT0/INTR,
LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK#
The Topology 2C CMOS LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK#
signals should implement a point-to-point connection between the Intel 82801DBM ICH4-M and the
processor. The routing guidelines allow both signals to be routed as either micro-strip or strip-lines
using 55
± 15% characteristic trace impedance. No additional motherboard components are necessary
for this topology.
Figure 22. Routing Illustration for Topology 2C
Intel
Pentium M
processor
Intel
ICH4-M
L1
Table 13. Layout Recommendations for Topology 2C
L1
Transmission Line Type
0.5” – 12.0”
Micro-strip
0.5” – 12.0”
Strip-line
