System Memory Design Guidelines (DDR-SDRAM)
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Intel
®
855PM Chipset Platform Design Guide
6.1.
DDR 200/266/333 MHz System Memory Topology and
Layout Design Guidelines
The Intel 855PM chipset’s Double Data Rate (DDR) SDRAM system memory interface implements the
low swing, high-speed, terminated SSTL_2 topology.
This section contains information and details on the DDR topologies, the DDR layout and routing
guidelines, and the DDR power delivery requirements that will provide for a robust DDR solution on an
system incorporating the Intel 855PM chipset.
Caution:
DDR System Memory Topologies for all signal groups have a relatively high via usage, please take this
into consideration for the board layout as the vias and the anti-pad for the via could restrict power
delivery to the SO-DIMMs.
Note:
Simulations performed for motherboard strip-line, simulations account for different propagation delays
in strip-line only and
not
accounted for in micro-strip. The simulated motherboard
r was 3.8 and 4.5.
Note:
Intel has conducted simulations for 2x8 SO-DIMMs that are based on the 1x8 raw card B populated
with Dual Die Package (DDP) SDRAM parts based on 512-Mbit devices (two 256-Mbit dies within the
same package). For platform design details for supporting this memory type, see Section 6.1.6.
Note:
In the
JEDEC PC2100 DDR SDRAM Unbuffered SO-DIMM Reference Design Specification, Rev 1.0
, it
is noted that pin 89 and pin 91 (CK2 and CK2#) of the SO-DIMM connector are reserved for x72
modules or registered modules. By default, the Intel 855PM MCH does not drive 3
rd
SCK pair to non-
ECC memory modules. Therefore, it is important to make sure that the memory modules are not
expected to use all clock pairs. Intel design guidelines for non-ECC memory modules assume that only 2
of 3 SCK differential clock pairs available on the MCH are used. Intel design guidelines assume that
only ECC memory modules utilize three SCK differential clock pairs.
6.1.1.
Data Signals – SDQ[71:0], SDQS[8:0]
The Intel 855PM MCH data signals are source synchronous signals that include a 64-bit wide data bus,
8 check bits for Error Checking and Correction (ECC), and 9 data strobe signals. There is an associated
data strobe (DQS) for each data (DQ) and check bit (CB) group. This section summarizes the DQ/CB to
DQS matching.
The data signals include SDQ[71:0] and SDQS[8:0]. The data signal group routing starting from the
MCH is as follows. The data signals should transition immediately from an external layer to an internal
signal layer under the MCH. Keep to the same internal layer until transitioning back to an external layer
at the series resistor. If the series resistor is on the same side of the board as SO-DIMM0 then stay on
external layer and route to appropriate pad of SO-DIMM0. If it is necessary to return to an internal
layer return to same internal layer and then return to external layer immediately prior to appropriate pad
of SO-DIMM0. If the series resistor is on the opposite side of the board then either transition to same
external layer as SO-DIMM0 and route to appropriate pad of SO-DIMM0 or return to the same internal
layer and then return to external layer immediately prior to the appropriate pad of SO-DIMM0. Continue
the route for the SO-DIMM0 pad by returning to same internal layer and transition to an external layer
immediately prior to the appropriate pad of SO-DIMM1. To connect the parallel termination resistor
either remain on same external layer as SO-DIMM1 and connect the parallel termination resistor,
transition to external layer on opposite of the board as the SO-DIMM1 and connect the parallel
