Platform Power Requirements
R
108
Intel
®
855PM Chipset Platform Design Guide
Figure 59. Processor Core Power Delivery and Decoupling Concept
South/Legacy Side
Pentium M Silicon Die
SKT
VR
FEED
Rsense
35x10uF
0805
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
9
6
8
9
3
PKG
VCC-CORE
4x220uF
SP Cap
North Side
VSS
Signals
+
-
+
Intel Pentium M Processor
Silicon Die
South/Legacy Side
Pentium M Silicon Die
SKT
VR
FEED
Rsense
35x10uF
0805
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
9
6
8
9
3
PKG
VCC-CORE
4x220uF
SP Cap
North Side
VSS
Signals
+
-
+
Intel Pentium M Processor
Silicon Die
In this example, bulk-decoupling 220-
F SP capacitors (according to V
CC-CORE
recommended
decoupling guidelines) are placed on the north side of the secondary side layer in the processor V
CC-CORE
power delivery corridor. Notice the VRM feed point (sense resistor connection) is on the positive
terminal side of the 220-
F SP capacitors. Both V
CC-CORE
and ground vias are used on both sides of the
SP capacitors’ positive terminal side in order to reduce the inductance of the capacitor connection as
illustrated by the current flow loop area in Figure 59. If the VR feed is on the negative side of the SP
capacitors then both V
CC-CORE
and GND stitching vias will be needed on both the positive and negative
terminals of the capacitor to reduce the effective inductance of the capacitor.
Layers 1 (primary side layer), 3, 5, 6, and (secondary side layer) 8 are used for V
CC-CORE
current feeding
while referencing Layers 2, 4, and 7 (ground planes) with a small dielectric separation (see Figure 2 in
Section 3.1). These layers are solid ground planes in the areas under the processor package outline and
where the decoupling capacitors are placed. This results in a reduction in effective loop inductance. For
the recommended layout examples shown in Figure 59, Figure 60, Figure 61, and Figure 62, a low
inductance value of ~41 pH is achieved. Bulk decoupling capacitors respond too slowly to handle the
fast current transients of the processor. For this reason, 0805 mid frequency decoupling capacitors are
added on the primary and secondary side. Some are placed under the package outline of the processor
while the rest are placed in the periphery of the processor along the AF signal row of the pin-map where
a majority of the V
CC-CORE
power pins are found. A 4-mil power plane separation between the secondary
side power plane flood and Layer 7 ground while using the 0805 capacitors significantly reduces the
inductance of these capacitors. Results from a 3D field solver simulation suggest that an ESL of 600-pH
per capacitor can be used to help achieve the specific layout style described above. The ESL of the 0805
capacitors is a very critical parameter, thus the layout style shown in the recommendation below should
be closely followed. To stress the importance of 0805 capacitors that result in an ESL of 600 pH, it can
be compared to ~1.2 nH ESL for 1206 form factor capacitors. Please note that the 0805 capacitors have
V
CC-CORE
and ground vias on both negative and positive terminals similar to the 220-
F SP capacitors in
order to achieve a low inductance connection.
