Platform Power Requirements
R
Intel
®
855PM Chipset Platform Design Guide
97
5.3.2.2. V
CC-CORE
Power Sequencing
There is only one enable pin, VR_ON, used to enable the outputs of the voltage regulator. When
VR_ON is low, all output voltage rails (V
CC-CORE
, V
CCP,
and V
CC_MCH
) are driven to a 0-V state. When
VR_ON is high, V
CCP
, V
CC_MCH
and V
CC-CORE
are commanded ramp up at the same time. Figure 48
illustrates the power on sequencing timing.
Figure 48. Power On Sequencing Timing Diagram
V
VID
VR_ON
V
V
CC_MCH
MCH_PWRGD
IMVP4_PWRGD
CCP
CC-CORE
- 12%
t
MCH-PWRGD
t
BOOT
t
BOOT-VID-TR
CLK_ENABLE#
See Note 1.
t
CPU_PWRGD
See Note 1.
V
BOOT
V
VID
t
SFT_START_VCC
-12%
-12%
Vccp_UP
CPU_UP
t
Vccp_UP
t
CPU_UP
NOTES:
1.
Desired, but not required feature of a processor and chipset regulator controller. If not implemented by the
controller, both the CLK_ENABLE# and the t
CPU-PWRGD
timer must be implemented by platform control logic.
2.
Figure 48 depicts a number of signals that may or may not be platform visible.
See Section 11.4 for platform power sequencing details and timing requirements.
5.4. V
CCP
Output Requirements
The V
CCP
output voltage rail provides power to the FSB rail for the Intel Pentium M/Intel Celeron M
processor, the Intel 855PM MCH, the 82801DBM ICH4-M, and ITP700FLEX debug port if it is used.
For the ICH4-M, this rail is known as V
CPU_IO.
The voltage regulator can be programmed via an external
