Platform Clock Routing Guidelines
R
232
Intel
®
855PM Chipset Platform Design Guide
10.2.
Clock Group Topology and Layout Routing Guidelines
10.2.1.
HOST_CLK Clock Group
The clock synthesizer provides three pairs of 100-MHz differential clock outputs utilizing a 0.7-V
voltage swing. The 100-MHz differential clocks are driven to the Intel Pentium M/Intel Celeron M
processor, the Intel 855PM MCH, and the processor debug port with the topology shown in the figure
below.
The clock driver differential bus output structure is a “Current Mode Current Steering” output which
develops a clock signal by alternately steering a programmable constant current to the external
termination resistors Rt. The resulting amplitude is determined by multiplying IOUT by the value of Rt.
The current IOUT is programmable by a resistor and an internal multiplication factor so the amplitude of
the clock signal can be adjusted for different values of Rt to match impedances or to accommodate
future load requirements.
The recommended termination for the differential bus clock is a “Source Shunt termination.” Refer to
Figure 129 for an illustration of this terminology scheme. Parallel Rt resistors perform a dual function,
converting the current output of the clock driver to a voltage and matching the driver output impedance
to the transmission line. The series resistors Rs provide isolation from the clock driver’s output
parasitics, which would otherwise appear in parallel with the termination resistor Rt.
The value of Rt should be selected to match the characteristic impedance of the system board and Rs
should be 33
± 5%. Simulations have shown that Rs values above 33
provide no benefit to signal
integrity but only degrade the edge rate.
The MULT0 pin (CK-408 pin #43) should be pulled-up through a 10 k
to VCC – setting the
multiplication factor to 6.
The IREF pin (CK-408 pin # 42) should be tied to ground through a 475
± 1 % resistor – making the
IREF 2.32 mA.
Figure 129. Source Shunt Termination Topology
L1'
L1
Rs
L2
L2'
L3
L3'
L4
L4'
Clock
Driver
CPU or
MCH
Rs
Rt
Rt
