System Overview
R
Intel
®
855PM Chipset Platform Design Guide
25
2.2. Intel
®
Pentium
®
M Processor/Intel
®
Celeron
®
M
Processor
2.2.1. Architectural
Features
Supports Intel Architecture with Dynamic Execution
High performance, low-power core
On-die, primary 32-kB instruction cache and 32-kB write-back data cache
On-die, second level cache with Advanced Transfer Cache Architecture
2-MB for Intel Pentium M Processor on 90nm process with 2-MB L2 Cache
1-MB for Intel Pentium M Processor
512-kB for Intel Celeron M Processor
Advanced Branch Prediction and Data Prefetch Logic
Streaming SIMD Extensions 2 (SSE2)
400-MHz, Source-Synchronous Front Side Bus
Advanced Power Management features including Enhanced Intel SpeedStep technology (not
supported by Intel Celeron M processor)
2.2.1.1. Packaging/Power
478-pin, Micro-FCPGA and 479-ball Micro-FCBGA packages
V
CC-CORE
:
¾
Refer to
Intel
®
Pentium
®
M Processor Datasheet
,
Intel® Pentium® M Processor on 90nm
process with 2-MB L2 Cache Datasheet
and
Intel
®
Celeron
®
M Processor Datasheet
for
V
CC-CORE
voltages
VCCA:
¾
Intel Pentium M processor and Intel Celeron M processor: 1.8 V
¾
Intel Pentium M processor on 90nm process with 2-MB L2 Cache: 1.8 V or 1.5 V
V
CCP
(1.05 V)
2.3.
Intel 855PM Memory Controller Hub (MCH)
2.3.1.
Front Side Bus Support
Optimized for the Intel Pentium M processor / Intel Celeron M processor in 478-pin Micro-FCPGA
and 479-ball Micro-FCBGA packages
AGTL+ bus driver technology with integrated GTL termination resistors (gated AGTL+ receivers
for reduced power)
