Platform Clock Routing Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
237
10.2.3.
AGPCLK Clock Group
The driver is the clock synthesizer 66-MHz clock output buffer and the receiver is the 66-MHz clock
input buffer at the AGP device. Note that the goal is to have minimal (~ 0) skew between this clock and
the clocks in the clock group CLK66.
Figure 132. AGPCLK to AGP Connector Topology
A
R1
Clock
Driver
AGP
Device
B
C
AGP
Connector
Trace on AGP
Card
Figure 133. AGPCLK to AGP Device Down Topology
A
R1
Clock
Driver
AGP
Device
B
