FSB Design Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
65
4.1.7.
GTLREF Layout and Routing Recommendations
There is one AGTL+ reference voltage pin on the processor, GTLREF, which is used to set the
reference voltage level for the AGTL+ signals (GTLREF). The reference voltage must be supplied to the
GTLREF signal, pin AD26 of the processor pin-map. The voltage level that needs to be supplied to
GTLREF must be equal to 2/3 * V
CCP
± 2%. The Intel 855PM MCH also requires a reference voltage
(MCH_GTLREF) to be supplied to its HVREF[4:0] pins. The GTLREF voltage divider for both the
processor and MCH cannot be shared. Thus, both the processor and MCH must have their own locally
generated GTLREF networks. Figure 29 shows the recommended topology for generating GTLREF for
Intel Pentium M processor using a R1 = 1 k
± 1% and R2 = 2 k
± 1% resistive divider.
Since the input buffer trip point is set by the 2/3* V
CCP
on GTLREF and to allow tracking of V
CCP
voltage fluctuations,
no
decoupling should be placed on the GTLREF pin. The node between R1 and R2
(GTLREF) should be connected to the GTLREF pin of processor with a Zo = 55
trace shorter than
0.5 inches. Space any other switching signals away from GTLREF with a minimum separation of 25
mils. Do not allow signal lines to use the GTLREF routing as part of their return path (i.e. do not allow
the GTLREF routing to create splits or discontinuities in the reference planes of the FSB signals).
Figure 29. Processor GTLREF Voltage Divider Network
GTLREF
(pin AD26)
Intel
Pentium M
processor
RSVD
(pin E26)
RSVD
(pin AC1)
RSVD
(pin G1)
GTLREF
R1
1K
1%
R2
2K
1%
+VCCP
< 1/2"
Zo = 55
Ω
trace
