I/O Subsystem
R
Intel
®
855PM Chipset Platform Design Guide
201
Figure 109. SMBUS 2.0/SMLink Protocol
Intel
ICH4-M
Host Controller and
Slave Interface
SMBus
SMBCLK
SPD Data
Temperature on
Thermal Sensor
Network
Interface Card
on PCI Bus
Microcontroller
Motherboard
LAN
Controller
Wire OR
(optional)
SMLink0
SMLink1
SMLink
SMBDATA
SMbus-SMlink_IF
Note:
Intel does not support external access of the ICH4-M’s Integrated LAN Controller via the SMLink
interface. Also, Intel does not support access of the ICH4-M’s SMBus Slave Interface by the ICH4-M’s
SMBus Host Controller. Refer to the
Intel
®
82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
Datasheet
functionality descriptions of the SMLink and SMBus interface.
9.6.1.
SMBus Architecture and Design Considerations
9.6.1.1.
SMBus Design Considerations
There is not a single SMBus design solution that will work for all platforms. One must consider the total
bus capacitance and device capabilities when designing SMBus segments. Routing SMBus to the PCI
slots makes the design process even more challenging since they add so much capacitance to the bus.
This extra capacitance has a large affect on the bus time constant which in turn affects the bus rise and
fall times.
Primary considerations in the design process are:
1.
Device class (High/Low power). Most designs use primarily high power devices.
2.
Are there devices that must run in S3?
3.
Amount of V
CC
_
SUSPEND
current available, i.e. minimizing load of V
CC
_
SUSPEND.
