Platform Power Requirements
R
110
Intel
®
855PM Chipset Platform Design Guide
processor socket. To allow good current flow from the SP capacitors to the north side of the V
CC-CORE
corridor pins, Intel recommends that these eight, 10-
F 0805 capacitors be spaced 100 mils apart from
each other even if the motherboard design rules allow tighter spacing. The 100-mil horizontal spacing
allows some V
CC-CORE
flood in between the capacitor ground pads (as illustrated in Figure 61) as well as
additional connections to internal Layers 3, 5, and 6 as illustrated in Figure 62. An additional nine, 10-
µF, 0805 capacitors are placed along the Y signal row of the processor pins on the secondary side below
the V
CC-CORE
“north corridor” pins under the shadow of the socket cavity. These nine capacitors are
spaced 90 mils apart. Each of these nine 0805 capacitors have a pair of V
CC-CORE
and GND stitching vias
next to both their positive and negative terminals. The stitching vias connect to the internal ground and
V
CC-CORE
planes respectively. The positive terminal V
CC-CORE
and GND stitching vias are shared with the
AA signal row of the processor’s V
CC-CORE
and ground pins. A wide V
CC-CORE
power delivery corridor
flood on the secondary side of the motherboard connects the 0805 ceramic and SP capacitors that are
placed to the north of the processor socket and the nine capacitors that are placed under the shadow of
the socket cavity on the secondary side. The flood is as wide as the whole AF signal row and should
connect to all the V
CC-CORE
pins in signal rows Y, W, V, and U as illustrated in Figure 61.
The remaining nine (out of thirty-two) 10-
F, 0805 (see Figure 60) capacitors are on the secondary side
are used to decouple the remainder of the twenty-four V
CC-CORE
/GND pin pairs on the south side of the
processor socket. These capacitors are placed along signal row G of the processor pins with a 90-mil (or
smaller) pitch. Each of the nine capacitors has a pair of V
CC-CORE
and GND stitching vias on both sides
of their terminals. Five out of nine capacitors share positive terminals with V
CC-CORE
and GND stitching
via connections with signal row F’s V
CC-CORE
and GND pins. The remaining four capacitors are placed
next to the V
CCP
pins of signal row F and have their own V
CC-CORE
vias but do share GND stitching vias.
As shown on the secondary side of Figure 60, a wide V
CC-CORE
flood connects the positive terminal of
these nine capacitors to all twenty-four V
CC-CORE
pins of the processor pin-map on the south side
including the V
CC-CORE
pins of signal rows K, J, H, and G. The reason for interruption of the V
CC-CORE
flood on the secondary side between the north and south sides is to allow the V
CCP
corridor connection
between the DATA and ADDR sides of the processor socket.
The primary side view in Figure 60 depicts two wide V
CC-CORE
floods that connect from the V
CC-CORE
stitching vias of the nine capacitors next to their negative terminal to the V
CC-CORE
pins of the two
clusters of the twenty-four V
CC-CORE
pins in rows K, J, H, G, F, E, and D of the processor pin-map. Note
the specific arrangement of the vias for the V
CC-CORE
dog bones to allow connection of all V
CC-CORE
BGA
balls in this cluster of twenty-four pins to the V
CC-CORE
flood shapes on the primary.
As described above in Figure 60, the V
CC-CORE
floods are isolated between the north and south sides of
the V
CC-CORE
pins of the processor socket on both the primary and secondary sides. The reason for the
discontinuity of the V
CC-CORE
floods on the primary and secondary sides is to facilitate V
CCP
power
delivery. Consequently, this allows the V
CCP
corridor connections between the DATA and ADDR sides
of the processor socket on the secondary side and the V
CCP
flood for all DATA, ADDR, and Legacy side
V
CCP
pins on the primary side (see Figure 60). In reality, the north and south sides of the V
CC-CORE
floods
are bridged by means of V
CC-CORE
planes in Layers 3, 5, and 6 as illustrated in Figure 62. Layers 3, 5,
and 6 connect the V
CC-CORE
stitching vias next to the negative terminals of the nine capacitors on the
north side with the V
CC-CORE
stitching vias next to the negative terminals of the nine capacitors on the
south side. Layers 3, 5, and 6 V
CC-CORE
corridors utilize the fact that there are no FSB signals routed
under the shadow of the processor socket cavity. All the V
CC-CORE
pins of the processor pin-map should
connect to the internal V
CC-CORE
planes of Layers 3, 5, and 6. Special attention should be give to not
route any of the FSB or any other signal in a way that would block V
CC-CORE
connections to all the V
CC-
CORE
power pins of the processor socket in Layers 3, 5, and 6. Figure 62 also shows how the V
CC-CORE
planes on Layers 3, 5, and 6 make an uninterrupted connection all the way from the SP capacitors and
sense resistors in the north side of the V
CC-CORE
corridor up to the south side of the twenty-four V
CC-CORE
pins of the processor socket. This continuous connection is imperative on all three internal layers since
