AGP Port Design Guidelines
R
176
Intel
®
855PM Chipset Platform Design Guide
7.3.7.
AGP VDDQ and VREF
AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics
controller. VDDQ is the interface voltage. The external graphics controller may
ONLY
power the Intel
855PM MCH AGP I/O buffers with 1.5-V VDDQ power pins.
7.3.8.
VREF Generation for AGP 2.0 (2X and 4X)
7.3.8.1.
1.5-V AGP Interface (2X/4X)
In order to account for potential differences between VDDQ and GND at the Intel 855PM MCH and
graphics controller, both devices use
source generated Vref
. That is, the Vref signal is generated at the
graphics controller and
sent
to the MCH and another Vref is generated at the MCH and
sent
to the
graphics controller.
Both the graphics controller and the MCH are required to generate Vref. The voltage divider networks
consist of AC and DC elements. The reference voltage that should be supplied to the Vref pins of the
MCH and the graphics controller is ½ * VDDQ. Two 1-k
± 1% resistors can be used to divide VDDQ
down to the necessary voltage level.
The Vref divider network should be placed as close to the AGP interface as is practical to get the benefit
of the common mode power supply effects. However, the trace spacing around the Vref signals must be
a minimum of 25 mils to reduce crosstalk and maintain signal integrity.
7.3.9. AGP
Compensation
The Intel 855PM MCH AGP interface supports resistive buffer compensation. For Printed Circuit
Boards with characteristics impedance of 55
, tie the GRCOMP pin to a 36.5
± 1% pull-down
resistor (to ground) via a 10-mil wide, very short (
0.5 inches) trace.
