System Memory Design Guidelines (DDR-SDRAM)
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Intel
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855PM Chipset Platform Design Guide
The DRAM Clock Control Disable Register (DCLKDIS: I/O Address 2E-2Fh) provides the capability to
enable and disable the CS/CKE and SCK signals to unpopulated SO-DIMMs. Although DDR SO-
DIMM connectors may provide motherboard lands for three clock pairs, Intel design recommendations
only support non-ECC SO-DIMMs that require two pairs. The MCH provides the flexibility to route any
differential clock pair to any SCK clock pair on the SO-DIMMs provided that the BIOS enables/disables
these clocks appropriately (e.g. the MCH’s SCK0 pair can be routed either to the SO-DIMM’s SCK0
pair or any other pair such as SCK1 or SCK2, etc.). By default, the enable/disable bits for the clock pairs
are set to ‘1’ and are disabled or tri-stated. To further reduce EMI/noise and save power, the SCK clock
pair pins of the MCH that are normally routed to ECC devices on ECC memory modules can be left as
no connects.
On platforms where ECC memory is supported, it is important that all relevant SDQ, SDQS, and SCK
signals to the SO-DIMMs be disabled when the system is populated with only non-ECC or a
combination of ECC and non-ECC memory. In such cases, the registers mentioned above must be
programmed appropriately.
6.4.2.
DDR Memory ECC Functionality Disable
It is imperative that systems that do not support ECC memory ensure the SCK clock pairs that are
normally sent to ECC SO-DIMMs be disabled. If the SCK clock pairs associated with the check bit
signals were left floating in a non-ECC memory only system and ECC memory was used in one or more
of the SO-DIMM slots, this could cause the ECC device on the SO-DIMM to be enabled. If SDQ[71:64]
is disabled/tri-stated or not routed, then these floating inputs can cause the ECC device to draw current
and potentially compromise the ECC device.
Previous revisions of this design guide provided guidelines that required additional hardware
termination to address the potential issue of floating inputs on an ECC SO-DIMM when populated in a
non-ECC memory only system. Since then, further analysis has been done and the new recommendation
is that
no hardware termination is required
on the SDQ[71:64], SDQS8, and SCK clock pair inputs of
the SO-DIMM connector.
This simplifies and provides the most reasonable hardware design recommendation that offers tradeoffs
between protecting any ECC memory inadvertently populated into the system vs. utilizing all physical
memory available in a system while incurring no power penalty.
6.5. System
Memory
Compensation
See Section 11.5.4 for details.
6.6. SMVREF
Generation
See Section 11.5.3.1 for details.
6.7.
DDR Power Delivery
See Section 11.5 for details.
