Platform Clock Routing Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
243
10.2.7.
CLK14 Clock Group
The driver is the clock synthesizer 14.318-MHz clock output buffer and the receiver is the 14.318-MHz
clock input buffer at the ICH4-M and SIO. Note that the clocks within this group should have minimal
skew (~ 0) between each other, however each of the clocks in this group is asynchronous to clocks of
any other group.
Figure 138. CLK14 Group Topology
A
R1
Clock
Driver
ICH4-M, SIO
B
Table 70. CLK14 Group Routing Guidelines
Parameter
Routing Guidelines
Figure
Notes
Signal Group
CLK14
1
Motherboard Topology
Point-to-Point
Reference Plane
Ground Referenced (Contiguous over entire
length)
Characteristic Trace Impedance (Zo)
55
± 15%
Trace Width
5 mils
Trace to Space Ratio
1:2 (e.g. 5 mils trace 10 mils space)
Group Spacing
Isolation spacing from non-Clock signals =
10 mils minimum
Trace Length – A
Min = 0 inches
Max = 0.50 inches
Figure 138
Trace Length – B
Min = 4.0 inches
Max = 8.50 inches
Figure 138
Series Termination Resistor (R1)
33
± 5%
Figure 138
Skew Requirements
Minimal skew (~ 0) between CLK14 group
and other groups, however the CLK14 group
is asynchronous to all other groups
NOTE:
Recommended resistor values and trace lengths may change in a later revision of the design guide.
10.2.8.
CK-408 Clock Chip Decoupling
See Section 11.7.9 for details.
