System Memory Design Guidelines (DDR-SDRAM)
R
Intel
®
855PM Chipset Platform Design Guide
131
6.1.1.2.
Strobe to Clock Length Matching Requirements
The data strobe signals may be up to 1.0 inches shorter or up to 0.5 inches longer than their associated
differential clock pairs.
Note:
Using this formula is made simpler by routing all clocks to the associated SO-DIMM the same length,
for example SCK/SCK#[2:0] all being the same length.
Length matching equation for SO-DIMM0:
X
1
= SCK/SCK#[2:0] = MCH p L1 of Figure 72
Y
1
= SDQS[8:0] = MCH p L1 + Rs L2 of Figure 72 where:
( Y
1
– 0.5” )
X
1
( Y
1
+ 1.0” )
Length matching equation for SO-DIMM1:
X
2
= SCK/SCK#[5:3] = MCH p L1 of Figure 72
Y
2
= SDQS[8:0] = MCH p L1 + Rs L2 + L3 of Figure 72 where:
( Y
2
– 0.5” )
X
2
( Y
2
+ 1.0” )
For example if the total clock length of SCK/SCK#[2:0](X
1
) is 3.5 inches then the length of all data
strobe signal routing to SO-DIMM0 must be between 2.5 inches to 4.0 inches, if SCK/SCK#[5:3](X
2
) is
4.5 inches then the length of all control signal route to SO-DIMM1 must be between 3.5 inches to 5.0
inches. Figure 74 depicts the length matching requirements between the DQS and clock signals.
The MCH package lengths for clocks and strobes
must
be taken into account for routing length
matching.
If clocks to each SO-DIMM are routed to different lengths due to allowable tolerance, then the
strobe to clock length requirement must be met for all clock lengths. For example if the clock pairs
to SO-DIMM0 are routed at 1.975 inches for CLK0/CLK0#, 2.000 inches for CLK1/CLK1#, and
2.025 inches for CLK2/CLK2# then the strobes length (DQS) to SO-DIMM0 must be routed
between 1.025 inches to and 2.475 inches. If the CLK to one SO-DIMM is all equal in length, 2.00
inches for example then the strobes (DQS) can be routed between 1.00 inches to 2.50 inches.
Refer to Section 4.4 for package trace length data.
