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Intel

855PM Chipset Platform Design Guide

5.7.

Voltage Regulator Topology ........................................................................................100

5.8.

Voltage Regulator Design Recommendations ............................................................100

5.8.1.

High Current Path, Top MOSFET Turned ON .............................................101

5.8.2.

High Current Paths During Abrupt Load Current Changes .........................101

5.8.3.

High Current Paths During Switching Dead Time........................................102

5.8.4.

High Current Path with Bottom MOSFET(s) Turned ON .............................102

5.8.5.

General Layout Recommendations .............................................................103

5.9.

Processor Decoupling Recommendations ..................................................................104

5.9.1.

Transient Response .....................................................................................104

5.9.2.

High Frequency, Mid Frequency, and Bulk Decoupling...............................105

5.9.3.

Processor Core Voltage Plane and Decoupling ..........................................106

5.9.4.

Intel Pentium M Processor / Intel Celeron M Processor
and Intel 855PM MCH V

CCP

Voltage Plane and Decoupling........................114

5.9.4.1.

Processor V

CCP

Voltage Plane and Decoupling............................114

5.9.4.2.

Intel 855PM MCH V

CCP

Voltage Plane and Decoupling................118

5.9.5.

Intel 855PM MCH Core Voltage Plane and Decoupling ..............................119

System Memory Design Guidelines (DDR-SDRAM)................................................................125

6.1.

DDR 200/266/333 MHz System Memory Topology and Layout Design Guidelines ...126

6.1.1.

Data Signals – SDQ[71:0], SDQS[8:0].........................................................126

6.1.1.1.

Data to Strobe Length Matching Requirements............................129

6.1.1.2.

Strobe to Clock Length Matching Requirements ..........................131

6.1.1.3.

Data Routing Example ..................................................................133

6.1.1.4.

Support for Small Form Factor Design DDR Data Bus Routing ...134

6.1.2.

Control Signals – SCKE[3:0], SCS#[3:0] .....................................................134

6.1.2.1.

Control to Clock Length Matching Requirements .........................136

6.1.2.2.

Control Routing Example ..............................................................138

6.1.3.

Command Signals – SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#...........139

6.1.3.1.

Command Topology 1 Solution.....................................................139

6.1.3.1.1.

Routing Description for Command Topology 1...........139

6.1.3.1.2.

Command Topology 1 to Clock Length Matching
Requirements..............................................................141

6.1.3.1.3.

Command Topology 1 Routing Example ....................143

6.1.3.2.

Command Topology 2 Solution.....................................................144

6.1.3.2.1.

Routing Description for Command Topology 2...........144

6.1.3.2.2.

Command Topology 2 to Clock Length Matching
Requirements..............................................................146

6.1.3.2.3.

Command Topology 2 Routing Example ....................148

6.1.4.

Clock Signals – SCK[5:0], SCK#[5:0] ..........................................................149

6.1.4.1.

Clock Signal Length Matching Requirements...............................151

6.1.4.1.1.

Clock Routing Example...............................................154

6.1.4.2.

Intel 855PM Chipset High Density Memory Support ....................155

6.1.5.

Feedback – RCVENOUT#, RCVENIN#.......................................................155

6.1.5.1.

RCVEN# Routing Example ...........................................................156

6.1.6.

Support for “DDP Stacked” SO-DIMM Modules ..........................................157

6.1.7.

Recommended Design Option to Support PC2700 DDR SDRAM
with Existing PC1600 and PC2100 Intel 855PM Platforms .........................158

6.1.7.1.

Shortened Data Signal Group Trace Length ................................158

6.1.7.1.1.

Supporting PC2700 Based on an Existing PC Platform
Layout .........................................................................158

6.1.7.1.2.

Additional Design Considerations for Adapting Intel
855PM DDR 200/266 MHz Platforms To Support
PC2700 .......................................................................159

6.2.

Intel 855PM MCH DDR Signal Package Lengths .......................................................160

Summary of Contents for 855PM

Page 1: ...Intel 855PM Chipset Platform Design Guide For use with Intel Pentium M and Intel Celeron M Processors May 2004 Revision Number 003 R Document Number 252614 003...

Page 2: ...t rely on any Intel provided information as either an endorsement or recommendation of any particular system design characteristics Intel may make changes to specifications and product descriptions at...

Page 3: ...tack up Routing and Spacing Assumptions 33 4 1 1 1 Trace Space to Trace Reference Plane Separation Ratio 33 4 1 1 2 Trace Space to Trace Width Ratio 34 4 1 1 3 Recommended Stack up Calculated Coupling...

Page 4: ...3 Onboard Debug Port Routing Guidelines 77 4 3 1 Recommended Onboard ITP700FLEX Implementation 78 4 3 1 1 ITP Signal Routing Guidelines 78 4 3 1 2 ITP Signal Routing Example 82 4 3 1 3 ITP_CLK Routing...

Page 5: ...port for Small Form Factor Design DDR Data Bus Routing 134 6 1 2 Control Signals SCKE 3 0 SCS 3 0 134 6 1 2 1 Control to Clock Length Matching Requirements 136 6 1 2 2 Control Routing Example 138 6 1...

Page 6: ...0 7 3 2 2 Trace Spacing Requirements 171 7 3 2 3 Trace Length Mismatch Requirements 172 7 3 3 AGP Clock Skew 173 7 3 4 AGP Signal Noise Decoupling Guidelines 173 7 3 5 AGP Routing Ground Reference 174...

Page 7: ...199 9 5 I O APIC I O Advanced Programmable Interrupt Controller 199 9 6 SMBus 2 0 SMLink Interface 200 9 6 1 SMBus Architecture and Design Considerations 201 9 6 1 1 SMBus Design Considerations 201 9...

Page 8: ...Signal Isolation 222 9 9 6 1 3 Magnetics Module General Power and Ground Plane Considerations 223 9 9 6 2 Common Physical Layout Issues 224 9 10 Power Management Interface 225 9 10 1 SYS_RESET Usage M...

Page 9: ...ing Resume 263 11 6 Clock Driver Power Delivery Guidelines 263 11 7 Decoupling Recommendations 265 11 7 1 Processor Decoupling Guidelines 265 11 7 2 Intel 855PM MCH Decoupling Guidelines 265 11 7 3 In...

Page 10: ...VREF Reference Voltage Dividers 304 14 8 ICH4 M Checklist 306 14 8 1 ICH4 M Resistor Recommendations 306 14 8 2 GPIO 308 14 8 3 AGP Busy Stop Design Requirements 309 14 8 4 System Management Bus SMBu...

Page 11: ...gure 21 DPSLP Layout Routing Example 57 Figure 22 Routing Illustration for Topology 2C 58 Figure 23 Routing Illustration for Topology 3 59 Figure 24 Voltage Translation Circuit 60 Figure 25 Processor...

Page 12: ...nded Layout Example 118 Figure 68 Intel 855PM MCH VCCP Power Delivery Recommended Layout Zoom In View 119 Figure 69 VCC MCH Power Delivery and Decoupling Concept 121 Figure 70 VCC MCH Power Planes and...

Page 13: ...Section 213 Figure 118 Single Solution Interconnect 214 Figure 119 LAN_CLK Routing Example 215 Figure 120 Intel 82562ET Intel 82562EM Termination 217 Figure 121 Critical Dimensions for Component Plac...

Page 14: ...r SMVREF 1 0 295 Figure 154 Intel 855PM MCH HSWNG 1 0 Reference Voltage Generation Circuit 299 Figure 155 Intel 855PM MCH HVREF 4 0 Generation Circuit 299 Figure 156 AGPREF Implementation On Intel CRB...

Page 15: ...114 Table 22 VCC MCH Decoupling Guidelines 120 Table 23 Intel 855PM Chipset DDR Signal Groups 125 Table 24 Data Signal Group Routing Guidelines 127 Table 25 SDQ 71 0 to SDQS 8 0 Length Mismatch Mappin...

Page 16: ...able 69 USBCLK Routing Guidelines 242 Table 70 CLK14 Group Routing Guidelines 243 Table 71 Power Management States 248 Table 72 Timing Sequence Parameters for Figure 140 250 Table 73 DDR Power Up Init...

Page 17: ...pdated design guidelines for supporting PC2700 333 MHz DDR SDRAM Transition from Intel 855PM DDR 266 200 MHz Chipset to Intel 855PM DDR 200 266 333 MHz Chipset Design Guidelines System Memory SMVREF D...

Page 18: ...R 18 Intel 855PM Chipset Platform Design Guide This page intentionally left blank...

Page 19: ...Chipset Memory Controller Hub for mobile platforms Also referred to as MCH 855PM Chipset Refers to the platform consists of Intel 855PM Chipset Memory Controller Hub MCH and Intel 82801 DBM Chipset I...

Page 20: ...on PLC Platform LAN Connect RTC Real Time Clock SMBus System Management Bus A two wire interface through which various system components can communicate SPD Serial Presence Detect S PDIF Sony Phillips...

Page 21: ...design mobile datashts 252337 htm Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M Specification Update http developer intel com design chipsets specupdt Intel 82802AB 82802AC Firmware Hub FWH Datash...

Page 22: ...Introduction R 22 Intel 855PM Chipset Platform Design Guide This page intentionally left blank...

Page 23: ...alidated to work with all of the Intel Centrino mobile technology components and is able to connect to 802 11 Wi Fi certified access points It also supports advanced wireless LAN security including Ci...

Page 24: ...r I O IDE 2 AC97 PCI Bus PCI Devices Hub Interface 1 0 Intel 82801DBM 421 BGA ICH4 M Intel 855PM MCH 593 Micro FCBGA Codecs FWH AGP Graphics Controller AGP 4X 2X 1 5V 400 MHz FSB USB2 0 1 1 6 200 266...

Page 25: ...ed Power Management features including Enhanced Intel SpeedStep technology not supported by Intel Celeron M processor 2 2 1 1 Packaging Power 478 pin Micro FCPGA and 479 ball Micro FCBGA packages VCC...

Page 26: ...orts up to 16 simultaneous open pages Support for SO DIMM Serial Presence Detect SPD scheme via SMBus interface STR power management support via self refresh mode using CKE 2 3 3 Accelerated Graphics...

Page 27: ...V5REF 5 V V5REF_SUS 5 V VCCRTC VCCHI 1 8 V V_CPU_IO VCCP 1 05 V 2 5 Intel PRO Wireless Network Connection Ability to connect to 802 11 Wi Fi Certified networks Industry standard and extended wireless...

Page 28: ...mance and battery life 2 5 1 Packaging and Power Mini PCI Type 3B 59 45 mm x 44 45 mm x 5mm Mini PCI Type 3A 59 45 mm x 50 8 mm x 5 mm 3 3V 2 6 Firmware Hub FWH An integrated hardware Random Number Ge...

Page 29: ...ce to trace coupling the routing guidelines documented in this section should be followed Also all high speed impedance controlled signals e g FSB signals should have continuous GND referenced planes...

Page 30: ...ce the coupling to Layer 4 and Layer 5 is still significant especially true when thinner stack ups use balanced strip lines on internal layers these layers are converted to ground floods in the areas...

Page 31: ...he motherboard Due to the arrangement of the Intel Pentium M Processor Intel Celeron M Processor and Intel 855PM MCH pin maps GND vias placed near all GND lands will also be very close to high speed s...

Page 32: ...General Design Considerations R 32 Intel 855PM Chipset Platform Design Guide This page intentionally left blank...

Page 33: ...entium M Processor Datasheet Intel Pentium M Processor on 90nm process with 2 MB L2 Cache Datasheet or Intel Celeron M Processor Datasheet for a FSB signal list signal types and definitions Below are...

Page 34: ...xample v Trace Trace 3X v X 4 1 1 3 Recommended Stack up Calculated Coupling Model The importance of maintaining an adequate trace space to trace width ratio is to achieve the best signal quality poss...

Page 35: ...in mils or inches and is specific to the recommended motherboard stack up see Figure 2 However some length matching tolerances for signals listed in this design guide may be stated as a measurement of...

Page 36: ...al layers For external layers route using a 5 mil trace width and a 10 mil minimum spacing i e 15 mil pitch Practical cases of escape routing under the MCH or the processor package outline and near by...

Page 37: ...8 BR0 BREQ0 Strip line 1 0 6 5 55 15 4 8 DBSY DBSY Strip line 1 0 6 5 55 15 4 8 DEFER DEFER Strip line 1 0 6 5 55 15 4 8 DPWR DPWR Strip line 1 0 6 5 55 15 4 8 DRDY DRDY Strip line 1 0 6 5 55 15 4 8...

Page 38: ...REQ0 Micro strip 1 0 6 5 55 15 5 10 DBSY DBSY Micro strip 1 0 6 5 55 15 5 10 DEFER DEFER Micro strip 1 0 6 5 55 15 5 10 DPWR DPWR Micro strip 1 0 6 5 55 15 5 10 DRDY DRDY Micro strip 1 0 6 5 55 15 5 1...

Page 39: ...ide 39 Figure 6 Common Clock Signals Example Intel 855PM MCH Escape Routing COMMON Clock Signals HIT DEFER HITM DPSLP RESET PRIMARY SIDE Layer 6 DRDY TRDY BNR Figure 7 Common Clock Signals Example Pro...

Page 40: ...m M 855PM Intel 855PM MCH M COMMON Clock Signals Mother Board Layer 6 routing Pentium M 855PM Intel 855PM MCH M Intel Pentium M Intel Pentium M processor Intel 855PM MCH M MCH COMMON Clock Signals Mot...

Page 41: ...thickness line width and velocity of the signals will be uniform across a single layer of the stack up There is no guarantee of a relationship of dielectric thickness line width and velocity between l...

Page 42: ...S signals can reference ground planes on both Layer 2 and Layer 4 Note that in the socket cavity of the processor Layer 3 is used for VCC core power delivery to reduce the I R drop However outside of...

Page 43: ...rce Synchronous Data Robust operation of the 400 MHz source synchronous data signals require tight skew control For this reason these signals are split into matched groups as outlined in Table 3 All t...

Page 44: ...h 1 2 spacing when using the tighter trace impedance tolerance the data strobes must maintain 1 3 spacing In this case the processor s DSTBN 3 0 and DSTBP 3 0 strobe signals must be routed to the MCH...

Page 45: ...4 8 ADSTB 1 0 HADSTB 1 0 Strip line 0 5 6 5 55 15 4 12 4 1 3 4 Source Synchronous Signals Recommended Layout Example Figure 11 illustrates escape routing of the FSB source synchronous signals in the...

Page 46: ...signal routing and its coexistence with a robust power delivery layout solution Source synchronous signals are serpentine length matched on Layer 3 and Layer 6 in the area in between the processor and...

Page 47: ...IDE LAYER 3 VCCA 1 8v 100MHz CLKs A 16 3 REQ D 15 0 D 47 32 1 8v Decap HI 1 8v Branch VCCHA VCCGA LAYER 6 PRIMARY SIDE 1 2v 855PM Core A 31 17 D 31 16 D 63 48 1 2v 855PM MCH Core PRIMARY SIDE LAYER 3...

Page 48: ...47 32 D 15 0 A 16 3 REQ A 31 17 D 63 48 D 31 16 PRIMARY SIDE PRIMARY SIDE PRIMARY SIDE LAYER 3 LAYER 6 PRIMARY SIDE PRIMARY SIDE PRIMARY SIDE PRIMARY SIDE LAYER 3 LAYER 3 LAYER 6 LAYER 6 VCCA 1 8v VC...

Page 49: ...ntium M processor Intel 855PM MCH M Intel Pentium M processor Intel 855PM MCH M Intel Pentium M processor Intel 855PM MCH M Intel Pentium M processor Intel 855PM MCH M MCH MCH 855PM 855PM L3 L6 Pentiu...

Page 50: ...nes The serpentines have to use the same 1 3 spacing as the rest of the routing It will be useful to make the traces 16 32 mils longer than needed in this stage It is also important that there should...

Page 51: ...Reference Length REFERENCE LENGTH 5950 STARTING LENGTH 6012 62 2 31 4 1 4 Asynchronous Signals 4 1 4 1 Topologies The following sections describe the topologies and layout recommendations for the Asy...

Page 52: ...ance Series resistor R1 is a dampening resistor for reducing overshoot undershoot reflections on the transmission line The pull up voltage for termination resistor Rtt is VCCP 1 05 V Due to the depend...

Page 53: ...el recommends that the THERMTRIP signal of the processor be routed to the THRMTRIP signal of the ICH4 M The ICH4 M s THRMTRIP signal is a new signal to the I O controller hub architecture that allows...

Page 54: ...e placement of Rs with respect to Q1 The placement of Rs a distance L3 before the Q1 BJT is a specific implementation of the generalized voltage translator circuit shown in Figure 24 Rs should be plac...

Page 55: ...or strip lines using 55 15 characteristic trace impedance The pull up voltage for termination resistor Rtt is VCCP 1 05 V Note that the Intel ICH4 M s CPUPWRGD signal should be routed point to point t...

Page 56: ...ce from the processor pin Figure 20 Routing Illustration for Topology 2B Intel 855PM MCH L1 L2 Intel ICH4 M Intel Pentium M processor Table 12 Layout Recommendations for Topology 2B L1 L2 Transmission...

Page 57: ...M Secondary Side L6 From ICH4 M DPSLP 855PM Pentium M COMMON Clock Signals Intel Pentium M processor Intel 855PM MCH M Intel 855PM MCH From Intel ICH4 M Secondary Side L6 From ICH4 M DPSLP 855PM Pent...

Page 58: ...point to point connection between the Intel 82801DBM ICH4 M and the processor The routing guidelines allow both signals to be routed as either micro strip or strip lines using 55 15 characteristic tra...

Page 59: ...nslator is shown in Figure 23 Series resistor Rs is a component of the voltage translator logic circuit and serves as a driver isolation resistor Rs is shown separated by distance L3 from the first bi...

Page 60: ...es filtering for noise and electrical glitches A larger first stage collector resistor R1 can be used on the collector of Q1 however it will result in a slower response time to the output falling edge...

Page 61: ...at the end of the L2 line that is limited to a 12 inch maximum length Rs 22 6 1 should be placed right next to Rtt to minimize the routing between them in the vicinity of the ITP700FLEX connector to l...

Page 62: ...Figure 27 Processor RESET Signal Routing Example with ITP700FLEX Debug Port Pentium M 855PM GND VIA Layer 6 FORK ITPFLEX connector Secondary Side VCCP Rs Rtt CPU L2 L3 Rs L1 ITPFLEX CONNECTOR MCH M R...

Page 63: ...en the processor and MCH s BCLK 1 0 signals a similar transition from Layer 3 to the secondary side layer is done next to the MCH package outline Routing of the MCH s BCLK 1 0 signals on the secondary...

Page 64: ...BCLK 1 0 507mil on L8 ITP BCLK 1 0 ITP INTERPOSER BCLK 1 0 507mil on L8 GND Via Intel Pentium M processor Intel 855PM MCH M Intel 855PM MCH 855PM MCH BCLK 1 0 507mil on L8 Secondary Side L3 855PM Pent...

Page 65: ...Figure 29 shows the recommended topology for generating GTLREF for Intel Pentium M processor using a R1 1 k 1 and R2 2 k 1 resistive divider Since the input buffer trip point is set by the 2 3 VCCP o...

Page 66: ...lustrative purposes and are not routed Figure 30 Processor GTLREF Motherboard Layout PRIMARY SIDE Pin G1 Pin G1 Pin AG1 Pin AG1 GTLREF Zo 55 0 5 GTLREF Zo 55 0 5 R1 R1 R2 R2 VCCP VCCP Pin E26 Pin E26...

Page 67: ...cuit components are located on the secondary side to minimize motherboard space usage and optimize robustness of the connection Each of the AB16 AB12 and P8 HVREF pins has a decoupling capacitor C1 C2...

Page 68: ...ign Guidelines R 68 Intel 855PM Chipset Platform Design Guide Figure 32 Intel 855PM MCH HVREF 4 0 Motherboard Layout C1 R1 MCH_GTLREF SECONDARY SIDE LAYER 3 C3 1 8v PRIMARY SIDE MCH_GTLREF PRIMARY SID...

Page 69: ...y with a single GND via to stitch the GND planes The compact layout as shown in Figure 33 should be used to avoid excessive perforation of the VCCP plane power delivery Figure 33 illustrates how a 27...

Page 70: ...M VCCP to 855PM VCCP VCCP VCCP VCCP One GND Via One GND Via COMP 0 COMP 0 COMP 1 COMP 1 COMP 2 COMP 2 COMP 3 COMP 3 AA1 Y2 GND pins AA1 Y2 GND pins Pin AG1 Pin AG1 VCCA 1 8v VCCA 1 8v Figure 34 Proces...

Page 71: ...h a 27 4 1 resistor The maximum trace length from pin to resistor should be less than 0 5 inches long and includes the dog bone connection on the primary side from the BGA land to the dog bone via Thi...

Page 72: ...hes of their respective pins and connected with a 15 mil wide trace To avoid coupling with any other signals maintain a minimum of 25 mils of separation to other signals Figure 37 Intel 855PM MCH HSWN...

Page 73: ...l operation This signal has an internal pull up that straps the FSB for 100 MHz operation However a stuffing option for a 1 k 5 pull up to a 1 5 V source can be provided for testing purposes For detai...

Page 74: ...processor s strapping resistors To avoid interaction with FSB routing the TEST 3 1 signal resistors are placed on the secondary side of the motherboard To avoid GND via interaction with the FSB routi...

Page 75: ...SE and VSSSENSE both be routed with a Zo 55 15 trace of equal length Use 3 1 spacing between the routing for the two signals and all other signals should be a minimum of 25 mils preferably 50 mils fro...

Page 76: ...slips of a month or more The latter scenario represents the time needed to spin a board design and required assembly time to add an ITP port when it is absolutely required and other mechanical and rou...

Page 77: ...ould otherwise be in the keepout area can be relocated for debug purposes i e axial lead devices that can be de soldered and re soldered to the other side of the board parts that can be removed and bl...

Page 78: ...d For the purpose of this discussion on ITP700FLEX signal routing refer to Section 4 1 1 4 for more details on the signal propagation time to distance relationships for the length matching requirement...

Page 79: ...ET RESET RESET CPURESET ITPCLK 1 0 BCLK 1 0 BaniasCLK 1 0 OdemCLK 1 0 BCLK 1 0 BCLKp Intel Pentium M processor Intel 855PM MCH 54 9 1 1 05v 22 6 1 BPM 5 RESETITP 240 5 BCLKn 1 05v VTT 0 1uF VTT 150 5...

Page 80: ...or the BPM 4 0 signals Due to the length of the ITP700FLEX cable the length L2 of the BPM 4 0 signals on the motherboard should be limited to be shorter than 6 0 inches The BPM 4 0 signals length L2 s...

Page 81: ...transitions should be minimized If layout constraints require a routing layer transition any such transition should be accompanied with ground stitching vias placed within 100mils of the signal via w...

Page 82: ...e the ITP700FLEX debug port No need for any external components for the BPM 5 0 signals 4 Only required if DBA is used with any target system circuitry This signal may be left unconnected if unused 5...

Page 83: ...All other signals incorporate a straight forward routing methodology between the ITP700FLEX and processor pins 4 3 1 3 ITP_CLK Routing to ITP700FLEX Connector A layout example for ITP_CLK ITP_CLK rout...

Page 84: ...et Platform Design Guide Figure 42 ITP_CLK to ITP700FLEX Connector Layout Example PRIMARY SIDE LAYER 6 ITP_CLK ITP_CLK ITP_CLK CK 408 ITP700FLEX Connector 33 49 9 PRIMARY SIDE LAYER 6 ITP_CLK ITP_CLK...

Page 85: ...l it is only possible to depopulate the 22 6 1 series resistor The 54 9 1 pull up resistor is required for termination purposes if the routing for RESET is not modified RESET would be a long untermina...

Page 86: ...it should be routed with a 150 to 240 pull up resistor placed within 1 ns of the ITP connector See the ITP700 Debug Port Design Guide for more details on DBA usage 4 3 2 1 ITP_CLK Routing to ITP Inter...

Page 87: ...r socket Finally the 150 to 240 pull up resistor for the DBR output signal from processor socket may or may not be depopulated depending on how it affects the system reset logic that it is connected t...

Page 88: ...ing solution as part of the LAI 4 3 3 2 Electrical Considerations The LAI will also affect the electrical performance of the FSB Therefore it is critical to obtain electrical load models from each of...

Page 89: ...31 16 564 HD 31 16 958 DINV 1 564 DBI 1 958 DSTBP 1 564 HDSTBP 1 958 Data Group 2 DSTBN 1 564 HDSTBN 1 958 D 47 32 661 HD 47 32 760 DINV 2 661 DBI 2 760 DSTBP 2 661 HDSTBP 2 760 Data Group 3 DSTBN 2...

Page 90: ...ils MCH Signal Name MCH Package Trace Length mils DEFER 349 DEFER 544 DPWR 506 DPWR 365 DRDY 529 DRDY 627 HIT 420 HIT 533 HITM 368 HITM 611 LOCK 499 HLOCK 611 RS 0 576 RS 0 350 RS 1 524 RS 1 467 RS 2...

Page 91: ...silicon Since these PLLs are analog in nature they require quiet power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings...

Page 92: ...NDARY SIDE LAYER 3 To Pentium M VCCA VCCGA VCCHA HI 1 8V VCCGA VCCHA DO NOT SHORT SECONDARY SIDE LAYER 3 To Pentium M VCCA VCCGA VCCHA HI 1 8V VCCGA VCCHA DO NOT SHORT 5 2 2 Intel 855PM MCH PLL Voltag...

Page 93: ...A3 are placed on the primary side in the vicinity of the GTLREF circuit refer to Figure 30 No via is required to connect the VCCA3 side of the capacitors to the VCCA3 pin The groundside of the VCCA3 c...

Page 94: ...or Intel Pentium M Intel Celeron M Processor There are six voltage identification pins on the Intel Pentium M Intel Celeron M processor These signals can be used to support automatic selection of VCC...

Page 95: ...Processor VID 5 0 Escape Routing Layout Example Secondary Side LAYER 3 LAYER 6 VID5 VID3 VID1 VID4 TO VRM VCC_CORE VCC_CORE VCCP To ITPFLEX ICH4 VCC_CORE VID2 VID0 VCCP To ITPFLEX ICH4 M Secondary Si...

Page 96: ...0 0 1 0 1 1 1 532 1 0 1 0 1 1 1 020 0 0 1 1 0 0 1 516 1 0 1 1 0 0 1 004 0 0 1 1 0 1 1 500 1 0 1 1 0 1 0 988 0 0 1 1 1 0 1 484 1 0 1 1 1 0 0 972 0 0 1 1 1 1 1 468 1 0 1 1 1 1 0 956 0 1 0 0 0 0 1 452 1...

Page 97: ...tCPU_PWRGD See Note 1 VBOOT VVID tSFT_START_VCC 12 12 Vccp_UP CPU_UP tVccp_UP tCPU_UP NOTES 1 Desired but not required feature of a processor and chipset regulator controller If not implemented by th...

Page 98: ...e regulator can be programmed via an external resistor network See Figure 50 VREF is used to set the highest output voltage in conjunction with the selection of R7 and R8 in the resistor network Figur...

Page 99: ...he Direct Current Resistance DCR of the power inductor has been reduced as well to lower the amount of power dissipation in the circuit s magnetic These technology improvements by themselves are not s...

Page 100: ...ETs connected in parallel but this solution usually leads to shoot through current as it is quite difficult to minimize the effect of the Gate Glitch phenomenon in the Synchronous MOSFET due to CGD ch...

Page 101: ...ound must also be adequate Figure 53 High Current Path With Top MOSFET Turned ON OutputVcc Feed back SCHOTTKY RLoad V_DC NMOS NMOS DRIVER CO TG BG Voltage Regulator ControlCircuitry 5 8 2 High Current...

Page 102: ...ath during the time that both top and bottom MOSFETs are OFF This is termed Dead Time During Dead Time there is a high current flow through the inductor processor ground and the Schottky diode The dio...

Page 103: ...the voltage drop across the sense resistor with a Kelvin connection The two feedback traces do not handle a high current but must be of equal lengths to get an accurate load measurement Connect the f...

Page 104: ...to the processor power and ground pins 5 9 1 Transient Response The inductance of the motherboard power planes slows the voltage regulator s ability to respond quickly to a current transient Decoupli...

Page 105: ...tial step the current may ramp continually within 9 clocks thus reaching an estimated ICCMAX of 25 A It should be noted that current consumption of Intel Pentium M processor and Intel Celeron products...

Page 106: ...a motherboard power plane stack up that allows for both robust high frequency signals routing and robust VCC CORE power delivery The processor pin map is shown in Figure 58 for reference in the discu...

Page 107: ...107 Figure 58 Intel Pentium M Processor and Intel Celeron M ProcessorSocket Core Power Delivery Corridor 49 VCC GND Pairs 24 VCC GND Pairs VR Feed 49 VCC GND Pairs 24 VCC GND Pairs VR Feed A conceptu...

Page 108: ...while referencing Layers 2 4 and 7 ground planes with a small dielectric separation see Figure 2 in Section 3 1 These layers are solid ground planes in the areas under the processor package outline an...

Page 109: ...An example layout implementation of the recommended VCC CORE decoupling guidelines is illustrated in Figure 60 Figure 61 and Figure 62 below Figure 60 and Figure 61 show how the four low frequency SP...

Page 110: ...erminal of these nine capacitors to all twenty four VCC CORE pins of the processor pin map on the south side including the VCC CORE pins of signal rows K J H and G The reason for interruption of the V...

Page 111: ...ended layout for the SP capacitor connections to minimize their inductance on the secondary side Layer 8 of the motherboard The VCC CORE pin side of the capacitor has two VCC CORE vias placed 82 mils...

Page 112: ...8 SS 4x220uF SP Cap 2 1 3 3 8x10uFx0805 VCCP To 855PM MCH Primary Side Secondary Side VCCP To 855PM 1 8v Sense Resistors VR Feed VCC_CORE VCCP VCCP To ITP VCC_CORE VCCP Cross Section View 9x10uFx0805...

Page 113: ...r Layer 6 Cross Sectional View L1 PS L2 GND L3 Sig L4 GND L5 PWR L6 Sig L7 GND L8 SS LAYER 3 ADDRESS DATA LAYER 5 LAYER 6 VCC CORE VCC CORE VCC CORE VR Feed ADDRESS DATA GND Ref for Layer 6 Cross Sect...

Page 114: ...oupling Guidelines Description Cap F ESR m ESL nH Notes Low Frequency Decoupling Polymer Covered Tantalum POSCAP Neocap KO Cap 2 x 150 F 36 m typ 2 2 5 nH 2 1 High Frequency Decoupling 0603 MLCC X7R P...

Page 115: ...RE flood that connects the south side 0805 capacitors with the twenty four VCC CORE pins on the south side of the processor pin map see secondary side of Figure 60 in Section 5 9 3 Thus the primary si...

Page 116: ...egacy Side Pentium M Silicon Die SKT L1 PS L2 GND L3 Sig L4 GND L5 PWR L6 Sig L7 GND L8 SS PKG North Side VSS VCCP 1 05v Short DATA ADDR Legacy Sides 150uF POSCAP 10x0 1uF 0603 VCCP 1 05v Short DATA A...

Page 117: ...E Primary SIDE VCC CORE VCCP DATA Side ADDR Side Legacy Side SECONDARY SIDE VCC CORE VCCP To ITP VCCP To 855PM ICH4 M 150uF POSCAP 10x0 1uF 0603 DATA Side ADDR Side VCCP GND Vias VCC CORE CROSS SECTIO...

Page 118: ...70mil 855PM Silicon Die 855PM Silicon Die PSB Side L1 PS L2 GND L3 Sig L4 GND L5 PWR L6 Sig L7 GND L8 SS L1 PS L2 GND L3 Sig L4 GND L5 PWR L6 Sig L7 GND L8 SS VCCP 1 05v 5x0 1uF 0603 150uF Secondary...

Page 119: ...r clarity refer to the Zoom In View picture of the capacitor placement on the MCH s secondary side on the inner row pin field as illustrated on the right side of Figure 68 One 150 F POSCAP placed on t...

Page 120: ...VCC MCH pins from the voltage regulator The vias also continue to the secondary side flood plane under the die shadow to provide a low inductance short between the 0805 and 0603 form factor high and m...

Page 121: ...855PM MCH M ODEM SIL ODEM SIL PSB Side DDR Side 2 5v 1 2v 1 05v L1 PS L2 GND L3 Sig L4 GND L5 PWR L6 Sig L7 GND L8 SS 855PM Silicon Die 855PM Silicon Die 0603 and 0805 Caps 2x150uF POSCAPS Intel 855PM...

Page 122: ...o small VCC MCH and ground floods on the secondary side that connect the vias to the POSCAP pads This is done to minimize the ESL of the POSCAPs in this connection In Figure 70 and Figure 71 placement...

Page 123: ...r 6 and the secondary side VCC MCH floods to the decoupling capacitors The groundside of the 0603 form factor 10 nF 15 nF 22 nF 47 nF and 220 nF capacitors connect to a ground ring on the secondary si...

Page 124: ...Platform Power Requirements R 124 Intel 855PM Chipset Platform Design Guide This page intentionally left blank...

Page 125: ...oller Hub MCH DDR 200 266 MHz Datasheet for details on the signals listed Table 23 Intel 855PM Chipset DDR Signal Groups Group Signal Name Description SDQ 63 0 Data Bus SDQ 71 64 Check Bits for ECC Fu...

Page 126: ...design guidelines for non ECC memory modules assume that only 2 of 3 SCK differential clock pairs available on the MCH are used Intel design guidelines assume that only ECC memory modules utilize thr...

Page 127: ...f the return current continuous Resistor packs are acceptable for the series Rs and parallel Rt data and strobe termination resistors but data and strobe signals can t be placed within the same R pack...

Page 128: ...DQS 8 0 SDQS 8 0 to SCK SCK 5 0 See Section 6 2 1for details NOTES 1 Recommended resistor values and trace lengths may change in a later revision of the design guide 2 Power distribution vias from Rt...

Page 129: ...e length to the pads of the SO DIMM1 connector L1 Rs Length L2 L3 For associated SDQS Length X and SDQ Byte Group Length Y the following must be met X 25 mils Y X 25 mils No length matching is require...

Page 130: ...m MCH M pin to SO DIMM0 connector pads DQ CB 0 DQ CB 1 DQ CB 2 DQ CB 3 DQS DQ CB 4 DQ CB 5 DQ CB 6 DQ CB 7 DQ CB Length Y X 25 mils DQ CB Length Y X 25 mils DQS Length X SO DIMM0 SO DIMM1 Intel 855PM...

Page 131: ...then the length of all data strobe signal routing to SO DIMM0 must be between 2 5 inches to 4 0 inches if SCK SCK 5 3 X2 is 4 5 inches then the length of all control signal route to SO DIMM1 must be b...

Page 132: ...all Motherboard Trace Lengths SDQS 8 0 SCK 2 0 SCK 2 0 Note Lengths are measured from MCH M pad to SO DIMM0 connector pads DQS Length Y SCK SCK 2 0 Length X SO DIMM0 SO DIMM1 Intel 855PM MCH Package M...

Page 133: ...n red The majority of the Data signal route is on an internal layer both external layers can used for parallel termination R pack placement Figure 75 Data Signals Group Routing Example From Odem Data...

Page 134: ...DIMM0 122 SCS 2 SO DIMM1 121 SCS 3 SO DIMM1 122 SCKE 0 SO DIMM0 96 SCKE 1 SO DIMM0 95 SCKE 2 SO DIMM1 96 SCKE 3 SO DIMM1 95 The control signal group routing starting from MCH is as follows The control...

Page 135: ...pace ratio 1 2 e g 4 mil trace to 8 mil space Group Spacing Isolation spacing for non DDR related signals 20 mils minimum Trace Length L1 MCH Control Signal Ball to SO DIMM Pad Min 0 5 inches Max 5 0...

Page 136: ...ching equation for SO DIMM1 X2 SCK SCK 5 3 Y2 SCS 3 2 and SCKE 3 2 L1of Figure 76 where Y2 1 0 X2 Y2 0 5 For example if the clock length of SCK SCK 2 0 X1 is 3 5 inches then the length of all control...

Page 137: ...therboard Trace Lengths SCS 1 0 SCKE 1 0 SCK 2 0 SCK 2 0 Note Lengths are measured from MCH M pins to SO DIMM0 connector pads CNTRL Length Y SCK SCK 2 0 Length X SO DIMM0 SO DIMM1 Motherboard Trace Le...

Page 138: ...uting is shown in red Figure 78 Control Signals Group Routing Example From Odem Control Signals To Parallel Termination From Intel 855PM MCH M From Odem Control Signals To Parallel Termination From In...

Page 139: ...via transition for SO DIMM0 continue the signal route on the same internal layer to the series termination resistor Rs collocated to SO DIMM1 At this resistor the signal should transition to an extern...

Page 140: ...gnal Ball to First SO DIMM Pad Min 1 0 inch Max 4 0 inches Figure 79 3 5 Trace Length L2 First SO DIMM Pad to Series Resistor Pad Max 1 1 inches Figure 79 3 Trace Length L3 Series Resistor Pad to Seco...

Page 141: ...th matching equation for SO DIMM1 X2 SCK SCK 5 3 Y2 Command Signals L1 L2 Rs Length L3 of Figure 79 where Y2 1 0 X2 Y2 0 5 For example if the clock length of SCK SCK 2 0 X1 is 5 0 inches then the leng...

Page 142: ...ce Lengths SCK 2 0 SCK 2 0 Note CMD Lengths are measured from MCH M pins to SO DIMM0 connector pads CMD Length Y SCK SCK 2 0 Length X SO DIMM0 SO DIMM1 Intel 855PM MCH Package SCK 5 3 SCK 5 3 SCK SCK...

Page 143: ...g Example Figure 81 is an example of a board routing for the Command signal group Command routing is shown in red Figure 81 Command Signals Topology 1 Routing Example FromOdem Series Dampening Resisto...

Page 144: ...mination resistor If sharing the via or using the opposite side of the board is not possible continue on the same internal layer and route to the external layer immediately prior to the termination re...

Page 145: ...1 0 inches Figure 82 3 Trace Length L3 Series Resistor Load to Second SO DIMM Pad Min 0 4 inches Max 1 75 inches Figure 82 3 Trace Length L4 Second SO DIMM Pad to Parallel Resistor Pad Max 0 25 inche...

Page 146: ...5 Length matching equation for SO DIMM1 X2 SCK SCK 5 3 Y2 Command Signals L1 L3 of Figure 82 where Y2 1 0 X2 Y2 0 5 For example if the clock length of SCK SCK 2 0 X1 is 5 0 inches then the length of...

Page 147: ...ce Lengths SMA 12 0 SBS 1 0 RAS CAS WE SCK 2 0 SCK 2 0 Note CMD Lengths are measured from MCH M pins to SO DIMM0 connector pads SCK SCK 2 0 Length X SO DIMM0 SO DIMM1 Motherboard Trace Lengths SCK 5 3...

Page 148: ...Resistors On reverse side of the board then the SO DIMMs Could be RPacks From Intel 855PM MCH M From Odem Command Signals Series Resistors On reverse side of the board then the SO DIMMs Could be RPack...

Page 149: ...0 DDR SDRAM Unbuffered SO DIMM Reference Design Specification This changing of clock numbering from MCH to SO DIMMs may require additional BIOS setting changes Swapping SCK and SCK within a differenti...

Page 150: ...ck pairs are equal in length plus tolerance and the 3 SO DIMM1 clock pairs are equal in length plus tolerance See Section 6 1 4 1 for details Clock Pair to Pair tolerance 25 mils SCK to SCK tolerance...

Page 151: ...ential clock pairs motherboard routing must be matched to 25 mils Each SCK to SCK pair motherboard routing must be matched to 10 mils Figure 86 and Figure 87 depict the length matching requirement bet...

Page 152: ...Length X0 SCK 0 Length X0 SCK1 Length X1 SCK 1 Length X1 SCK2 Length X2 SCK 2 Length X2 SO DIMM0 SO DIMM1 Motherboard Trace Lengths Intel 855PM MCH Package Note Lengths are measured from MCH M pin to...

Page 153: ...CK 2 SO DIMM0 SO DIMM1 SCK SCK 3 SCK SCK 4 SCK SCK 5 Note Lengths are measured from MCH M pin to SO DIMM1 connector pads Motherboard Trace Lengths Intel 855PM MCH Package Max X0 X0 X1 X1 X2 X2 Min X0...

Page 154: ...ple of a board routing for the Clock signal group Clock routing is shown in red Figure 88 Clock Signal Routing Example Odem Clocks SO DIMM0 SO DIMM1 Intel 855PM MCH M Odem Clocks SO DIMM0 SO DIMM1 Int...

Page 155: ...to gate the strobe inputs for read data There are two pins on the MCH to facilitate the use of RCVEN The RCVENOUT pin is an output of the MCH and the RCVENIN pin is an input to the MCH RCVENOUT must...

Page 156: ...H Feedback Signal Pin to Signal Via Max 40 mils Figure 89 2 Trace Length L2 MCH RCVENOUT Signal Via to RCVENIN Signal Via Must 100 mils 5mils Figure 89 Trace Length L3 Signal Via to MCH Feedback Signa...

Page 157: ...n external layer Intel 855PM MCH M Intel 855PM MCH MCH Pin 6 1 6 Support for DDP Stacked SO DIMM Modules Simulations have been performed to verify the suitability of the DDR layout and routing guideli...

Page 158: ...ayout While the maximum length of L1 L2 L3 and L4 remains unchanged from previous revisions of this design guide the maximum overall length allowed from the MCH M to the second SO DIMM L1 Rs L2 L3 for...

Page 159: ...rms must also adhere to all other existing design guidelines for the DDR 200 MHz and 266 MHz platforms Table34 contains section references to all other existing design guidelines that need to be follo...

Page 160: ...Data Signal Name Intel 855PM MCH Package Trace Length mils Data Signal Name Intel 855PM MCH Package Trace Length mils DATA GROUP 1 DATA GROUP 6 SDQ 7 0 945 SDQ 47 40 732 SDQS 0 945 SDQS 5 732 DATA GR...

Page 161: ...r detection and single bit error correction This option to design for and support ECC DDR memory modules is dependent on design objectives By default ECC functionality is disabled on the platform For...

Page 162: ...be programmed appropriately 6 4 2 DDR Memory ECC Functionality Disable It is imperative that systems that do not support ECC memory ensure the SCK clock pairs that are normally sent to ECC SO DIMMs b...

Page 163: ...r the ETS pin and usage placement guidelines of the thermal sensors for maximum effectiveness Current third party vendor product offerings that may be suitable for the ETS pin application include ambi...

Page 164: ...nt signals Also any thermal design considerations e g proper ground flood placement underneath the external thermal sensor proper isolation of the differential signal routing for thermal diode applica...

Page 165: ...or on motherboard Best Location is sensor under S0 DIMM May not be mechanically feasible in all designs due to small gap between SO DIMM and motherboard 15mm 15mm Top View SO DIMM Side View SO DIMM Se...

Page 166: ...System Memory Design Guidelines DDR SDRAM R 166 Intel 855PM Chipset Platform Design Guide This page intentionally left blank...

Page 167: ...2X mode of AGP operation uses source synchronous data strobing During 4X operation the AGP interface uses differential source synchronous data strobing However differential source synchronous data str...

Page 168: ...n within the 2X 4X timing domain signals there are three sets of signals All signals in the 2X 4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spaci...

Page 169: ...0 SB_STB and SB_STB When the term data is used it refers to one of the three sets of data signals as in Table 37 When the term strobe is used it refers to one of the strobes as it relates to the data...

Page 170: ...st meet minimum and maximum trace length requirements 7 3 2 2X 4X Timing Domain Routing Guidelines 7 3 2 1 Trace Length Requirements for AGP 2X 4X These trace length guidelines apply to ALL of the sig...

Page 171: ...fer to Table 36 must be routed as documented in Table 39 They should be routed using 4 mil traces Additionally the signals can be routed with 5 mil spacing when breaking out of the Intel 855PM MCH The...

Page 172: ...gth 6 in 1 2 X X 0 1 in X 0 1 in The trace length minimum and maximum relative to strobe length should be applied to each set of 2X 4X timing domain signals independently That is if AD_STB0 and ADSTB0...

Page 173: ...ts on the clock edge that falls in the switching range The 1 ns skew budget is divided such that the motherboard is allotted 0 9 ns of clock skew the motherboard designer shall determine how the 0 9 n...

Page 174: ...all AGP signals be referenced to ground depending on the board layout In an ideal design the complete AGP interface signal field would be referenced to ground This recommendation is not specific to a...

Page 175: ...e Intel 855PM MCH has integrated pull ups to ensure that these signal do not float when there is no add in card in the connector 2 The Intel 855PM MCH does not implement the PERR and SERR signals Pull...

Page 176: ...nd sent to the graphics controller Both the graphics controller and the MCH are required to generate Vref The voltage divider networks consist of AC and DC elements The reference voltage that should b...

Page 177: ...le HI_STB and HI_STB are associated with the strobe signals Figure 94 Hub Interface Routing Example Intel ICH4 M Intel 855PM MCH CLK Synthesizer CLK66 CLK66 HI 10 0 HI_STB HI_STB 8 1 Hub Interface Com...

Page 178: ...each HI 7 0 signal must be matched to within 100 mils of the strobe signals Table 45 Hub Interface Signals Internal Layer Routing Summary Signal Max length inch Width mils Space mils Mismatch length m...

Page 179: ...n 8 within 300 mils from the package 8 3 2 External Layer Routing Traces should be routed 5 mils wide with 10 mils trace spacing 5 on 10 and 20 mils spacing from other non hub interface signals In ord...

Page 180: ...her the MCH or ICH4 M If the single HIREF divider is located more than 3 inches away locally generated hub interface reference voltage dividers should be used instead The reference voltage generated b...

Page 181: ...citors per each component i e the ICH4 M and MCH These capacitors should be placed within 150 mils from each package adjacent to the rows that contain the hub interface If the layout allows wide metal...

Page 182: ...Hub Interface R 182 Intel 855PM Chipset Platform Design Guide This page intentionally left blank...

Page 183: ...on the motherboard The additional resistor layout increases flexibility by offering stuffing options at a later date The IDE interface can be routed with 5 mil traces on 7 mil spaces and must be less...

Page 184: ...onnector 22 47 series resistors are required on RESET The correct value should be determined for each unique motherboard design based on signal quality An 8 2 k 10 k pull up resistor is required on IR...

Page 185: ...onnector 22 47 series resistors are required on RESET The correct value should be determined for each unique motherboard design based on signal quality An 8 2 k 10 k pull up resistor is required on IR...

Page 186: ...ted 9 1 4 1 Intel 82801DBM ICH4 M IDE Interface Tri State Feature The new IDE interface tri state capabilities of the Intel 82801DBM ICH4 M also include a number of configuration bits that must be pro...

Page 187: ...he IDE_CONFIG register B0 D31 F0 Offset 54h bits 19 18 or 17 16 to 10 10b This will cause all IDE outputs to the IDE drive to drive low rather than the default tri state which is useful during boot up...

Page 188: ...801DBM ICH4 M implements an AC 97 2 1 2 2 and 2 3 compliant digital controller Please contact your codec IHV Independent Hardware Vendor for information on 2 2 compliant products The AC 97 2 2 specifi...

Page 189: ...or for crystal or oscillator requirements AC_BIT_CLK is a 12 288 MHz clock driven by the primary codec to the digital controller ICH4 M and to any other codec present That clock is used as the time ba...

Page 190: ...on Resistance AC_BIT_CLK Signal Length Matching 5 on 5 L1 1 to 8 L3 L2 0 1 to 6 L3 0 1 to 0 4 L4 1 to 6 L3 R1 33 47 R2 Option 0 resistor for debugging purposes N A NOTES 1 Simulations were performed u...

Page 191: ...is best for the Sigmatel 9750 codec Figure 103 Intel 82801DBM ICH4 M AC 97 AC_SDIN Topology AC_SDIN2 Intel ICH4 M Y2 Codec Y1 AC_SDIN1 AC_SDIN0 R2 R2 AC97_SDATA_IN1 AC97_SDATA_IN0 Y1 Y1 Y3 Y3 AC97_SDA...

Page 192: ...rence pins Do not completely isolate the analog audio ground plane from the rest of the board ground plane There should be a single point 0 25 inches to 0 5 inches wide where the analog isolated groun...

Page 193: ...rimary Codec Secondary Codec Tertiary Codec Notes 1 Audio Audio Audio 1 2 Audio Audio Modem 1 3 Audio Audio Audio Modem 1 4 Audio Modem Audio 1 5 Audio Audio Modem Audio 1 6 Audio Modem Audio Audio 1...

Page 194: ...irst Maintain maximum possible distance between high speed clocks periodic signals to USB 2 0 differential pairs and any connector leaving the PCB i e I O connectors control and signal headers or powe...

Page 195: ...with the trace spacing needed to achieve 90 differential impedance Deviations will normally occur due to package breakout and routing to connector pins Just ensure the amount and length of the deviat...

Page 196: ...ld be trace length matched Max trace length mismatch between USB 2 0 signal pair should be no greater that 150 mils 9 4 1 6 USB 2 0 Trace Length Guidelines Table 53 USB 2 0 Trace Length Guidelines Wit...

Page 197: ...rated by the split They are also used to bridge or bypass power and ground planes close to where a high speed signal changes layers As an example of bridging plane splits a plane split that separates...

Page 198: ...print to provide a stuffing option in the event the choke is needed to pass EMI testing Figure 108 shows the schematic of a typical common mode choke and ESD suppression components The choke should be...

Page 199: ...on in case it is needed to pass ESD testing 9 5 I O APIC I O Advanced Programmable Interrupt Controller The Intel 82801DBM ICH4 M is designed to be backwards compatible with a number of the legacy int...

Page 200: ...e When using the Intel 82562EM Platform LAN Connect Component the ICH4 M s integrated LAN Controller will claim the SMLink heartbeat and event messages and send them out over the network An external A...

Page 201: ...H4 M Datasheet functionality descriptions of the SMLink and SMBus interface 9 6 1 SMBus Architecture and Design Considerations 9 6 1 1 SMBus Design Considerations There is not a single SMBus design so...

Page 202: ...al devices on the core supply This is accomplished by the use of a FET to isolate the devices powered by the core and suspend supplies See Figure 110 Figure 110 High Power Low Power Mixed VCC_SUSPEND...

Page 203: ...ance 2 pF inch per SO DIMM and 2 pF connector capacitance per SO DIMM 42 2 86 3 129 4 172 5 215 PCI Slots 6 Each PCI add in card is allowed up to 40 pF 3 pF per each connector 258 24 48 36 72 Bus Trac...

Page 204: ...decode there will be two devices positively decoding the same cycle 9 7 3 FWH INIT Voltage Compatibility The FWH INIT signal trip points need to be considered because they are NOT consistent among dif...

Page 205: ...7 5 FWH INIT Assertion Deassertion Timings Due to the large routing solution space and necessity of a voltage translator in the design of a FWH on Intel Pentium M Processor Intel Celeron M Processor a...

Page 206: ...Internal Oscillator RTCX1 SUSCLK Low Swing 32 768 kHz Sine Wave Source Full Swing 32 768 kHz Output Signal Intel For further information on the RTC please consult Application Note AP 728 ICH Family R...

Page 207: ...of the ICH4 RTCX1 is the Input to the Internal Oscillator RTCX2 is the feedback for the external crystal NOTES 1 The exact capacitor value needs to be based on what the crystal maker recommends Typica...

Page 208: ...on of Cload above the value of C1 C2 can be calculated to give the best accuracy closest to 32 768 kHz of the RTC circuit at room temperature However C2 can be chosen such that C2 C1 Then C1 can be tr...

Page 209: ...r 9 8 4 RTC External Battery Connections The RTC requires an external battery connection to maintain its functionality and its RAM while the Intel 82801DBM ICH4 M is not powered by the system Example...

Page 210: ...battery life and thereby the RTC accuracy 9 8 5 RTC External RTCRST Circuit Figure 116 RTCRST External Circuit for the ICH4 M RTC VCCSUS3_3 VccRTC 1 0uF 1K 0 1uF 180K RTCRST RTCRST CIRCUIT DIODE BATT...

Page 211: ...lter out most of AC signal noise that exists on this ball However the noise on this ball should be kept minimal in order to guarantee the stability of the RTC oscillation Probing VBIAS requires the sa...

Page 212: ...lert on LAN AoL Intel 82562ET 48 Pin SSOP LCI Basic 10 100 Ethernet Ethernet 10 100 connection Design guidelines are provided for each required interface and connection 9 9 1 Footprint Compatibility T...

Page 213: ...implement a platform LAN Connect device on a system motherboard It should not be treated as a specification and the system designer must ensure through simulations or other techniques that the system...

Page 214: ...ta signals must be equal to or no more than 0 5 inches 500 mils shorter than the LAN clock trace 9 9 2 2 Signal Routing and Layout Platform LAN Connect Interface signals must be carefully routed on th...

Page 215: ...impedance of 55 15 is strongly recommended otherwise signal integrity requirements may be violated 9 9 2 5 Line Termination Line termination mechanisms are not specified for the LAN Connect Interface...

Page 216: ...the effects of EMI clock sources should not be placed near I O ports or board edges Radiation from these devices may be coupled onto the I O ports or out of the system chassis Crystals should also be...

Page 217: ...nsions There are two dimensions to consider during layout Distance A from the line RJ 45 connector to the magnetics module and distance B from the Intel 82562ET or Intel 82562EM to the magnetics modul...

Page 218: ...traces requires that the distance between these components be closely observed In general any section of traces that is intended for use with high speed signals should observe proper termination prac...

Page 219: ...apacitor with an adjacent ground plane The signals can be routed through 75 resistors to the plane Stray energy on unused pins is then carried to the plane 9 9 3 5 2 Termination Plane Capacitance Inte...

Page 220: ...RST Logic 10 ms delay Rpack 100 5 Test_En Isol_Tck Isol_Ti Isol_Tex RSMRST To ICH5 FromICH5 There are four pins which are used to put the Intel 82562ET EM controller in different operating states Test...

Page 221: ...are specific to a 4 3 mil stack up Maintain constant symmetry and spacing between the traces within a differential pair Keep the signal trace lengths of a differential pair equal to each other Keep t...

Page 222: ...as practical Long and thin traces are more inductive and would reduce the intended effect of decoupling capacitors Also for similar reasons traces to I O signals and signal terminations should be as...

Page 223: ...ver a split plane If there are vacant areas on a ground or power plane avoid routing signals over the vacant area This will increase inductance and EMI radiation levels Separate noisy digital grounds...

Page 224: ...been fully tested for IEEE PLC conformance long cable BER and for emissions and immunity Inferior magnetics modules often have less common mode rejection and or no auto transformer in the transmit ch...

Page 225: ...SUS3_3 should also be implemented to ensure that no potential floating inputs to SYS_RESET cause a system reset The ICH4 M will debounce signals on this pin 16 ms and allow the SMBus to go idle before...

Page 226: ...h the CMOS signals of the processor For Intel Pentium M Intel Celeron M processor based systems the ICH4 M s V_CPU_IO rail uses the same 1 05 V voltage as the VCCP rails for the processor and Intel 85...

Page 227: ...system R Intel 855PM Chipset Platform Design Guide 227 Figure 127 Intel 82801DBM ICH4 M CPU CMOS Signals with CPU and FWH Intel Pentium M processor FWH INIT Output Signals FERR V_CPU_IO 1 05V Intel IC...

Page 228: ...I O Subsystem R 228 Intel 855PM Chipset Platform Design Guide This page intentionally left blank...

Page 229: ...more information on CK 408 compliance refer to the CK 408 Clock Synthesizer Driver Specification The following tables and figure list and detail the Intel 855PM MCH clock groups the platform system c...

Page 230: ...CPU CPU BCLK 1 CPU Debug Port BCLK 0 CPU Debug Port BCLK 1 CPU MCH BCLK 0 HOST_CLK CPU MCH BCLK 1 MCH 66IN CLK66 3V66 ICH4 M CLK66 AGPCLK 3V66 AGP Connector or AGP Device CLK PCIF ICH4 M PCICLK SIO PC...

Page 231: ...ctor PCI Connectors SIO FWH 100 MHz 66IN CLK 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz 48 MHz 14 318 MHz 33 MHz CLK66 PCICLK CLK48 CLK14 33 MHz 33 MHz 33 MHz 14 318 MHz 33 MHz CLK CLOCKI PCI_CLK CLK CLK CLK...

Page 232: ...values of Rt to match impedances or to accommodate future load requirements The recommended termination for the differential bus clock is a Source Shunt termination Refer to Figure 129 for an illustr...

Page 233: ...hes Max 0 20 inches Figure 129 14 Processor Routing Length L3 L3 Rt Node to Rt Min 0 inches Max 0 50 inches Figure 129 14 Processor Routing Length L4 L4 Rt Node to Receiver Min 2 0 inches Max 8 0 inch...

Page 234: ...l Length compensation for the processor socket and package delay is added to chipset routing to match electrical lengths between the chipset and the processor from the die pad of each Therefore the sy...

Page 235: ...tween routing layers is compensated in the traces to other agents 3 Do not place vias between adjacent complementary clock traces and avoid differential vias Vias placed in one half of a differential...

Page 236: ...ence Plane Ground Referenced Contiguous over entire length Characteristic Trace Impedance Zo 55 15 Trace Width 4 mils Trace to Space Ratio 1 5 e g 4 mils trace 20 mils space Group Spacing Isolation sp...

Page 237: ...buffer and the receiver is the 66 MHz clock input buffer at the AGP device Note that the goal is to have minimal 0 skew between this clock and the clocks in the clock group CLK66 Figure 132 AGPCLK to...

Page 238: ...ation Resistor R1 33 5 Figure 133 Skew Requirements Minimal skew 0 between AGPCLK and CLK66 group NOTES 1 Recommended resistor values and trace lengths may change in a later revision of the design gui...

Page 239: ...m Trace Length A Must be exactly trace length matched to CLK66 Trace A Figure 134 Trace Length B Must be exactly trace length matched to CLK66 Trace B Figure 134 Series Termination Resistor R1 33 5 Fi...

Page 240: ...e Width 5 mils Trace to Space Ratio 1 4 e g 5 mils trace 20 mils space Group Spacing Isolation spacing from non Clock signals 20 mils minimum Trace Length A Must be exactly trace length matched to CLK...

Page 241: ...e Width 5 mils Trace to Space Ratio 1 2 e g 5 mils trace 10 mils space Group Spacing Isolation spacing from non Clock signals 10 mils minimum Trace Length A Must be exactly trace length matched to CLK...

Page 242: ...Group USBCLK 1 Motherboard Topology Point to Point Reference Plane Ground Referenced Contiguous over entire length Characteristic Trace Impedance Zo 55 15 Trace Width 5 mils Trace to Space Ratio 1 2 e...

Page 243: ...Signal Group CLK14 1 Motherboard Topology Point to Point Reference Plane Ground Referenced Contiguous over entire length Characteristic Trace Impedance Zo 55 15 Trace Width 5 mils Trace to Space Rati...

Page 244: ...ace voltage 1 05 V 10 4 CK 408 PWRDWN Signal Connections For Intel Pentium M processor Intel Celeron M processor based systems that support the S1M state the PWRDWN input of the CK 408 clock chip is r...

Page 245: ...ic required to wake the system remain powered Standby power rails may or may not be powered depending on system design and the presence of AC or battery power S5 Soft Off The Soft Off state correspond...

Page 246: ...ion Note that the voltage on a dual power rail may be misleading 11 2 Platform Power Requirements The following figure shows the power delivery architecture for an example Intel 855PM chipset platform...

Page 247: ...VCC_CORE Processor VR VCCP PSB VR 1 6 2 1 GB s AGP4x 1 5v 1 06GB s 855PM MCH M VCC_MCH MCH VR V1 5S V1 8S V2 5 V1 25 AGP V1 5S V3 3S V5S V12S ICH4 M V1 5S V1 5 V1 8S V3 3S V3 3 V3 3LAN V5S 13 Bit Hub...

Page 248: ...SLP_S5 V ALW V V S Clocks FULL ON HIGH HIGH HIGH HIGH ON ON ON ON S1M POS LOW HIGH HIGH HIGH ON ON ON LOW S3 STR LOW LOW HIGH HIGH ON ON OFF OFF OFF S4 STD LOW LOW LOW HIGH ON ON OFF OFF OFF S5 Soft...

Page 249: ...rm Power Up Sequence VccSus Running SUSCLK SLP_S3 Vcc PWROK VGATE SUS_STAT PCIRST Frequency Straps STPCLK CPUSLP Strap Values Normal Operation Hub interface CPU Reset Complete message RSMRST RSM_PWROK...

Page 250: ...183a SLP_S5 inactive to SLP_S4 inactive 1 2 RTCCLK 139 T183b SLP_S4 inactive to SLP_S3 inactive 1 2 RTCCLK 139 T184 Vcc active to STPCLK CPUSLP STP_CPU STP_PCI SLP_S1 C3_STAT inactive and CPU Frequenc...

Page 251: ...sequencing rule This rule also applies to the stand by rails but in most platforms the VCCSUS3_3 rail is derived from the VCCSUS5 and therefore the VCCSUS3_3 rail will always come up after the VCCSUS...

Page 252: ...2 V5REF_SUS With 5V_ALWAYS Connection Option V5ALWAYS USB D V5REF_SUS1 V5REF_SUS2 USB D ICH4 M USB Power 5V GND Customer specific or Intel recommended USB interface circuits Customer specific or Intel...

Page 253: ...y to the processor must be stable for a minimum of 4 s before the ICH4 M s CPUPWRGOOD signal can be asserted to the processor s PWRGOOD input Similarly the RSTIN input of the MCH must be asserted by t...

Page 254: ...requirements as of publishing for this document This document is not the original source for these specifications Refer to the following documents for the latest details on voltage and current requir...

Page 255: ...ould be connected to 2 5 V and ground The ground trace should connect to a via that transitions to the ground plane The ground via should be placed as close to the ground pad as possible The 2 5 V tra...

Page 256: ...d be used not a percentage of the measured value Likewise percentages should be used where stated If not stated then either way is fine Voltage specifications are defined as either Absolute or Relativ...

Page 257: ...VDDQ VREF Vdd 2 0 050 V 2 5 V 8 2 0 050 V Voltage Nominal V 2 500 2 500 1 250 Tolerance 8 0 8 0 4 0 Tolerance V 0 200 0 200 0 050 Max Absolute Spec Value V 2 700 2 700 1 400 2 5V 8 2 0 050 V Min Abso...

Page 258: ...0 040 V 2 5 V 5 2 0 050 V 0 040 Voltage Nominal V 2 500 1 250 1 250 Tolerance 5 0 2 0 3 2 Tolerance V 0 125 0 025 0 040 Max Absolute Spec Value V 2 625 1 339 1 440 2 5 V 5 2 0 050 V 0 040 Min Absolute...

Page 259: ...that needs to be supplied to these pins must be equal to VCCSM 2 Note in Figure 144 that although SMVREF is generated from the 2 5 V supply a buffer is used as well A buffer has also been used to pro...

Page 260: ...ide voltage regulation within 2 Some sample calculations are shown in Table 79 it is not possible to maintain regulation within 2 using a resistive divider without using a resistor so small that the 2...

Page 261: ...y of 50 mV This basically means to use 1 resistors or better Table 81 Reference Distortion Due to Load Current R I A Vdroop V I 2 5 total 2 5 V 2R A 1 0 001 0 001 1 25 10 0 001 0 01 0 125 100 0 001 0...

Page 262: ...st be at least 50 mils wide The Data and Command signals should be terminated using one resistor per signal Resistor packs and 5 tolerant resistors are acceptable for this application Only signals fro...

Page 263: ...ive to switching noise induced by the other VDDs on the cock chip They are also sensitive to switching noise generated elsewhere in the system such as the CPU VRM The CLC pi filter should be designed...

Page 264: ...dd Vdd Vdd Vdd 48 MHz Vss 48 MHz Vss Vss Vdd Vss Vss Vss Vss Iref Vss XTAL_In XTAL_Out PCIF 0 PCIF 2 PCIF 1 PCI 0 PCI 3 PCI 2 PCI 1 PCI 6 PCI 5 PCI 4 66Buff0 3V66_2 66Buf f1 3V66_ 3 66Buf f2 3V66_ 4 6...

Page 265: ...2 VCCSM See Section 11 5 1 1 Decoupling Cap See Section 11 5 1 1 Place near balls See Section 11 5 1 VCCP See Section 5 9 4 Decoupling Cap See Table 21 Place near balls See Figure 64 Figure 66 11 7 3...

Page 266: ..._3 2 0 1 F Decoupling Cap Vss Place near balls E9 and F9 V_CPU_IO 1 0 1 F Decoupling Cap Vcc Place near ball AA23 VCC1_5 2 0 1 F Decoupling Cap Vss Place near balls K23 and C23 VCCSUS1_5 2 0 1 F Decou...

Page 267: ...nally the distance from any DDR termination resistor pin to a VTT capacitor pin must not exceed more then 100 mils 11 7 5 AGP Decoupling See Section 7 3 4 for details 11 7 6 Hub Interface Decoupling S...

Page 268: ...oupled through the decoupling caps to the VSS pins This method has been shown to provide the best clock performance The decoupling requirements for a CK 408 compliant clock synthesizer are as follows...

Page 269: ...S0 D0 2 15 5 mA N A N A N A N A VccLAN1_5 D3 2 13 mA 13 mA 4 mA 4 mA N A VccLAN3_3 S0 D0 2 9 2 mA N A N A N A N A VccLAN3_3 D3 2 2 1 mA 2 1 mA 2 1 mA 2 1 mA N A VccSUS1_5 1 67 5 mA 35 7 mA 8 4 mA 8 4...

Page 270: ...ife of the product It does not represent the expected power generated by a power virus The thermal design power number for the Intel 855PM MCH and Intel 82801DBM ICH4 M are listed below Table 86 Intel...

Page 271: ...s between Bluetooth and Intel PRO Wireless 2100 Although these traces do not need to match any length width or impedance constraints a typical width of 5 mils and spacing of 5 mils is recommended Pin...

Page 272: ...of using USB selective Suspend Support published in http www intel com design mobile platform downloads Power_Saving_USB_Selective_Suspend pdf 12 4 Wake on Bluetooth Requirements WoBT Wake on Bluetoo...

Page 273: ...rocessor and Intel Celeron M RSVD Signals The Intel Pentium M processor Intel Celeron M processor has a total of three TEST and seven RSVD signals that are Intel reserved in the pin map All other RSVD...

Page 274: ...uld be left as no connects The 1 k resistor should not be populated by default The location of the Intel reserved signals in the MCH pin map is listed in Table 89 The MCH s TESTIN signal is used manuf...

Page 275: ...ut information Note Unless otherwise specified the default tolerance on resistors is 5 Also note that the S reference after power rails such as VCC3_3 S indicates a switched rail u one that is powered...

Page 276: ...1 25S X Vcc1_5 V1 5S 1 5S_AGP X VccSus1_5 V1 5 V1 5ALWAYS X X 1 3 1 3 V1_5ALWAYS See VccSus1_5 X X X X Vcc1_8 V1 8S X VccSus2_5 V2 5_MCH V2 5DDR X X Vcc3_3 V3S V3 3S_ICH X VccSus3_3 V3 V3ALWAYS X X 1...

Page 277: ...ils 50 mils preferred away from any other toggling signal See section 4 1 8 placement and routing guidelines COMP 1 COMP 3 Pull down to GND 54 9 1 Resistor placed within 0 5 of CPU pin via a Zo 55 tra...

Page 278: ...placed near the system receiver Series resistor should be placed between the receiver and termination resistor Series resistor should have no stub when connecting to IERR trace from the CPU See Sectio...

Page 279: ...onnection to MCH If ITP700FLEX Is Used RESET forks out from the MCH to the CPU and ITP700FLEX 1 st branch connects the MCH point to point to the CPU 2 nd branch needs to be pulled up to VCCP through a...

Page 280: ...ND should be provided for testing purposes For normal operation resistor should be No Stuff THERMTRIP Pull up to VCCP 56 5 6 THERMTRIP is a 1 05 V tolerant signal and voltage translation logic may be...

Page 281: ...d be provided for testing purposes For normal operation resistor should be No Stuff Also a test point for a differential probe ground should be placed between the two termination resistors of VCCSENSE...

Page 282: ...REF Voltage Divider Network GTLREF pin AD26 Intel Pentium M processor RSVD pin E26 RSVD pin AC1 RSVD pin G1 GTLREF R1 1K 1 R2 2K 1 VCCP 1 2 Zo 55 trace Figure 149 Routing Illustration for INIT Intel P...

Page 283: ...ure 150 Voltage Translation Circuit 1 3K ohm 5 330 ohm 5 3 3V To Receiver From Driver 3904 3904 Q1 Q2 3 3V Rs R1 R2 330 ohm 5 Figure 151 Routing Illustration for PROCHOT Intel Pentium M Processor L1 L...

Page 284: ...should be placed within 1 ns of the ITP700FLEX ITP700FLEX supported Production Systems Leave this signal as NC No Connect See Section 4 3 1 1 and 4 3 1 4 for details DBR Pull up to target VCC or See...

Page 285: ...n ITP700FLEX supported Production Systems Parallel termination resistor placed within 2 0 of CPU pin See Section 4 3 1 1 and 4 3 1 4 for details TDO Pull up to VCCP 54 9 1 IF ITP700FLEX IS USED 22 6 1...

Page 286: ...parallel termination resistor ITP700FLEX supported Production Systems Parallel termination resistor placed within 2 0 of CPU pin See Section 4 3 1 1 and 4 3 1 4 for details VTAP VTT 1 0 Tie to VCCP Th...

Page 287: ...d to system reset logic e g SYS_RESET of ICH4 M Pull up resistor must be placed within 1ns of CPU socket ITP Interposer supported Production Systems Pull up may be required depending on impact to syst...

Page 288: ...ermal Sensor Platform recommendations and design guidelines provided by your diode thermal sensor vendor should be adhered to ensure proper operation of your thermal sensor 14 4 4 Decoupling Recommend...

Page 289: ...Platform Design Checklist R Intel 855PM Chipset Platform Design Guide 289 Decoupling Recommendations 1 Signal Configuration F Qty Notes 9 and decoupling...

Page 290: ...CPU clock pair to the ITP_CLK signals of the CPU socket Routing to ITP700FLEX NOT necessary CPU_STOP Point to point connection to the ICH4 M s STP_CPU signal DOT 33 If the signal is used one 33 serie...

Page 291: ...0 Pull up to Vcc3_3 1K USB 33 If the signal is used one 33 series resistor is required for each receiver If NOT used this signal can be left as NC No Connect XTAL_IN None See Notes Connect to XTAL_OUT...

Page 292: ...gure 152 Clock Power Down Implementation CLK_PWRDWN PM_SLP_S1 PM_SLP_S3 Vcc3_3Sus V3ALWAYS 14 5 2 CK 408 Decoupling Recommendation Platform recommendations and decoupling guidelines provided by your C...

Page 293: ...1 64 Pull up to Vcc1_25 DDR_Vtt See Notes 56 See Notes 10 See Notes See Section 6 1 1 for routing requirements If ECC is NOT Supported These signals can be left as NC No Connect SDQS 7 0 Pull up to Vc...

Page 294: ...routed to any SO DIMM provided that the BIOS understands the routing implementation Trace width option 2 inner layer trace width 7 mils is the recommended implementation for improved DDR timing margi...

Page 295: ...Platform Design Checklist R Intel 855PM Chipset Platform Design Guide 295 Figure 153 Reference Voltage Level for SMVREF 1 0 Vcc2_5 VccSus2_5 10k 1 1 10k 1 SMVREF Intel 855PM MCH SMVREF0 SMVREF1...

Page 296: ...5 0 in Section 14 6 1 1 If ECC Is NOT Supported These signals should be left as NC No Connect DQS 8 See Notes This signal is ECC related If ECC Is Supported This signal needs to be routed to MCH See...

Page 297: ...left as NC No Connect RESET DU See Notes This signal can be left as NC No Connect VDDID See Notes This signal can be left as NC No Connect DDR SO DIMM Interface Misc Signal SA 2 0 Tie to GND Connect...

Page 298: ...lled up to a 2 5 V source through a 8 2 k to 10 k See Section 6 8 for details Hub Interface Signals HSWNG 1 0 301 1 top 150 1 bottom Signal voltage level 1 3 VCCP R1a R1b 301 1 R2a R2b 150 1 C1a C1b 0...

Page 299: ...nce Voltage Generation Circuit R1a 301 1 R2a 150 1 C1a 0 1uF Intel 855PM MCH HSWNG 0 HSWNG 1 301 1 150 1 C1b 0 1uF VCCP VCCP HSWNG 0 HSWNG 1 Figure 155 Intel 855PM MCH HVREF 4 0 Generation Circuit R1...

Page 300: ...Pull up to Vcc1_8 36 5 1 HLRCOMP resistor value 2 3 board impedance HRCOMP 1 0 Pull down to GND 27 4 1 Each signal should be pulled down to ground through a 27 4 1 resistor with a Zo 27 4 trace Max t...

Page 301: ...to VCC_MCH 150 F 2 2 F 220 nF 47 nF 22 nF 15 nF 10 nF 2 1 1 1 1 1 1 See Section 5 9 5for details VCCGA VCCHA Tie to Vcc1_8 10 F 10 nF 1 1 VCCGA and VCCHA can both share a 10 F and 10nF decoupling capa...

Page 302: ...oltage divider if the divider is located within 3 from both the MCH and ICH4 M See Figure 157 and Section 8 4 for more details For each of the 3 signals a locally generated hub interface reference vol...

Page 303: ...l pull down External pull down is NOT required DEVSEL FRAME GNT IRDY REQ STOP TRDY PIPE RBF WBF See Notes Point to point connection to AGP controller MCH has an internal pull up External pull up is NO...

Page 304: ...Interface High Frequency Decoupling Recommendations 1 Pin Name Configuration F Qty Notes 9 Vcc1_5 Pull down to GND 0 01 F 6 Place a minimum of six 0 01 F within 70 mils of the outer row of balls on t...

Page 305: ...form Design Checklist R Intel 855PM Chipset Platform Design Guide 305 Figure 156 AGPREF Implementation On Intel CRB 1K 1K Vcc1_5 Intel 855PM MCH AGP 0 1uF 0 1uF Place near AGP Place near MCH Vrefcg AG...

Page 306: ...e rising edge of PWROK By default this signal is HIGH or strap function is DISABLE Strap function can be enabled by pulling down this signal to GND through a 1 k resistor IRDY Pull up to Vcc3_3 8 2 k...

Page 307: ...Damping Notes 9 PIRQ A D PIRQE GPIO2 PIRQF GPIO3 PIRQG GPIO4 PIRQH GPIO5 Pull up to Vcc3_3 See Notes 8 2 k External pull up is required for INT_PIRQ A D External pull up is required when muxed signal...

Page 308: ...ALERT GPIO 13 can be used as SMC_WAKE_SCI These pins are inputs Main power well GPIOs are 5 V tolerant except for GPIO 43 32 Resume power well GPIOs are not 5 V tolerant GPIO 23 16 Fixed as output onl...

Page 309: ...rnal AGP Graphics Controller C3_STAT No pull up pull down required See notes When an external AGP device is enabled this signal must be connected from ICH4 M to the external AGP Graphics Controller fo...

Page 310: ...ation Value of pull up resistor is also determined by line load Intel CRB uses 10K pull up resistor Please see Intel CRB schematics page 18 The SMBus and SMLink signals must be tied together externall...

Page 311: ...rements AC_SDIN 2 0 33 47 A series termination resistor R1 is required for the PRIMARY CODEC A series termination resistor is required for the SECONDARY R2 R1 and TERTIARY R3 R1 CODEC if the resistor...

Page 312: ...TC well input requires pull down to reduce leakage from coin cell battery in G3 Input must not float in G3 This signal should be connected to power monitoring logic and should go high no sooner than 1...

Page 313: ...Used If this signal is not connected to a driver then it is required to be terminated with a 8 2 k pull up to Vcc3_3 SYS_RESET Pull up to VccSus3_3 100 k if signal is not used Implementation of this s...

Page 314: ...ystem Pull up Pull down Series Damping Notes 9 OC 5 0 Pul lup to V3ALWAYS 10 k These signals are inputs into the ICH4 M and must not be left floating Pull up is required If an OC pin is not connected...

Page 315: ...viders 1 Pin Name System Pull up Pull down Notes 9 HIVREF See Notes HIVREF HI_VSWING and HI_REF MCH signal can share a common hub interface reference divider Also see Figure 157 For each of the 3 sign...

Page 316: ...ltage Divider Circuit Intel ICH4 M Intel 855PM MCH HIREF HIREF VCC HI 1 8V R1 C1 R2 C2 C1 HI_VSWING C1 NOTES R1 R2 100 to 150 C1 0 01 uF C2 0 1 uF Figure 158 Hub Interface with Locally Generated Refer...

Page 317: ...delay Any RC circuit which will result in the 18 25 ms delay is acceptable CLK_RTCX1 CLK_RTCX2 See notes Connect a 32 768 kHZ crystal oscillator across these pins with a 10 m resistor and use a decou...

Page 318: ...Sus 10M C1 C2 C3 R1 R2 Notes Reference Designators Arbitrarily Assigned 3 3V Sus is Active Whenever System Plugged In Vbatt is Voltage Provided By Battery VBIAS VCCRTC RTCX1 and RTCX2 are ICH4 M pins...

Page 319: ...See Notes Connect to LAN_RXD on the platform LAN Connect Device See Section 9 9 2 for routing requirements If LAN interface is not used leave the signal unconnected NC LAN_TXD 2 0 See Notes Connect t...

Page 320: ...s for series resistors can be implemented should the system designer have signal integrity concerns These signals have integrated series resistors NOTE Simulation data indicates that the integrated se...

Page 321: ...for series resistors can be implemented should the system designer have signal integrity concerns These signals have integrated series resistors NOTE Simulation data indicates that the integrated ser...

Page 322: ...s sampled on the rising edge of PWROK An integrated weak pull down is enabled only at boot reset Status of strap is readable via the NO_REBOOT bit D31 F0 Offset D4h bit 1 1 disabled 0 enabled normal o...

Page 323: ...to Vcc5 1 k One 0 1 F capacitor place near ball E7 is required for decoupling VCC5REFSUS1 See Notes One 0 1 F capacitor place near ball A16 is required for decoupling If Wake on USB from S3 and self...

Page 324: ...CONN E A Each signal requires a LC Pi filter that consists of one 0 1 F one 100 F and one ferrite bead in Intel CRB See Figure 160 Both caps on Pin 2 of ferrite bead Optimal decoupling achieve with 10...

Page 325: ...See Notes Can be connected directly to GND In Intel CRB each signal requires a 100 ohms pull down resistor IC See Notes In Intel CRB the signal requires a 10 kohms pull down resistor RST 100 In Intel...

Page 326: ...ndations LAN Resistor Recommendations Pin Name System Pull up Pull down Series Damping Notes 9 ISOL_EX ISOL_TCK ISOL_TI Pull up to VccSus3_3LAN 10 k All three signals are pulled up to VccSus3_3LAN thr...

Page 327: ...Recommendations 1 Signal Name Configuration F Qty Notes 9 VccLan3_3 Pull down to GND 0 1 F 4 7 F 4 2 VccLan_L3_3 Pull down to GND 0 1 F 4 7 F 1 1 LAN_X1 LAN_X2 Pull down to GND 22 pF 1 Each pin requir...

Page 328: ...Platform Design Checklist R 328 Intel 855PM Chipset Platform Design Guide This page intentionally left blank...

Page 329: ...Intel Customer Reference Board Schematics R Intel 855PM Chipset Platform Design Guide 329 15 Intel Customer Reference Board Schematics See the following page for customer reference board schematics...

Page 330: ...MDC Header FWH PG 14 PG 3 4 PG5 PG5 PG 6 7 8 PG 10 PG 10 PG9 PORT80 PS 2 SMC KBC Scan KB Hitachi H8S 2149 PS 2 LPC PM Headers LPC SLOT PG 15 16 17 PG 26 PG 26 PG 26 PG 25 PG 25 PG 24 PG 28 PG 31 PG 3...

Page 331: ...Termination voltage off in S4 S5 1 5V switched power rail off in S3 S5 1 5V always on power rail 1 5V power rail off in S4 S5 1 8V switched power rail off in S3 S5 2 5V power rail for DDR 3 3V always...

Page 332: ...P 4 5 7 15 16 17 37 39 42 VCCP 4 5 7 15 16 17 37 39 42 VCCP 4 5 7 15 16 17 37 39 42 VCCP 4 5 7 15 16 17 37 39 42 VCCP 4 5 7 15 16 17 37 39 42 VCCP 4 5 7 15 16 17 37 39 42 VCCP 4 5 7 15 16 17 37 39 42...

Page 333: ...SS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS187 VS...

Page 334: ...M2_ITP 3 H_BPM4_PRDY 3 ITP_DBRESET 3 41 CLK_ITP 14 CLK_ITP 14 V3 3S 9 10 14 15 17 18 20 23 28 30 31 32 33 36 37 38 41 42 V3 3S 9 10 14 15 17 18 20 23 28 30 31 32 33 36 37 38 41 42 V3 3S 9 10 14 15 17...

Page 335: ...4 10 M_RAS 10 11 12 M_CKE3_R 10 12 M_CKE0_R 10 12 42 M_CLK_DDR4 10 AGP_ST1 9 M_CLK_DDR0 10 M_CLK_DDR3 10 M_CLK_DDR3 10 AGP_ST0 9 M_CLK_DDR2 10 AGP_ST2 9 M_CLK_DDR1 10 AGP_GNT 9 M_CLK_DDR2 10 M_CLK_DDR...

Page 336: ...F10 F14 F16 F18 F22 G1 G29 H10 H12 H14 H16 H18 H20 H22 H24 H5 L25 L29 N23 M22 J6 K22 K24 K26 K7 H8 N26 M8 AB10 T8 G16 G10 G9 H7 H4 H3 G3 G2 L23 VCCAGP0 VCCAGP1 VCCAGP2 VCCAGP3 VCCAGP4 VCCAGP5 VCCAGP6...

Page 337: ...5 U17 U29 U4 V22 V6 W1 W26 W4 Y22 W8 A11 A15 A19 A23 A27 A3 A7 AB9 T16 U8 AB15 AB17 AB22 Y6 P16 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS15 VSS17 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28...

Page 338: ...1 42 V5S_AGP V1 5S_AGP V1 5S_AGP V1 5S_AGP V1 5S 4 6 7 17 41 V1 5 17 V3 3 7 15 17 20 24 27 29 32 34 36 40 41 V3 3S_AGP V3 3S 5 10 14 15 17 18 20 23 28 30 31 32 33 36 37 38 41 42 V1 5S 4 6 7 17 41 C201...

Page 339: ...15 27 39 51 63 75 87 103 125 137 149 159 161 173 185 4 16 28 38 40 52 64 76 88 90 104 126 138 150 162 174 186 85 123 124 200 201 202 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD...

Page 340: ...R_0 M_A_FR_3 M_A_FR_8 M_A5 M_A12 M_A_FR_11 M_A_FR_2 M_A_FR_1 M_A_FR_7 M_A0 M_A10 M_A7 M_A_FR_10 M_A_FR_4 M_A_FR_12 M_A_FR_5 M_A3 M_A_FR_9 M_A9 M_CB0 M_CB1 M_CB6 M_CB5 M_CB3 M_CB7 M_CB2 M_DQS_R4 M_DQS_...

Page 341: ...10 11 M_WE 6 10 11 M_DQS_R 8 0 10 11 M_CS0_R 6 10 42 M_CKE0_R 6 10 42 M_BS1 6 10 11 M_CS3_R 6 10 M_CKE2_R 6 10 M_BS0 6 10 11 M_CS1_R 6 10 42 M_CKE3_R 6 10 M_CKE1_R 6 10 42 M_CS2_R 6 10 V1 25S 6 13 40...

Page 342: ...0 0 1UF C572 0 1UF C279 150uF C573 0 1UF C566 0 1UF C262 150uF C548 0 1UF C484 0 1UF C264 150uF C580 0 1UF C540 0 1UF C590 0 1UF C530 0 1UF C571 0 1UF C533 0 1UF C513 0 1UF C581 0 1UF C486 0 1UF C565...

Page 343: ...R419 475_1 C265 NO_STUFF_10pF R146 1K C259 NO_STUFF_10pF R179 NO_STUFF_0 R138 49 9_1 C469 0 1UF RP24C 33 3 6 C470 0 1UF C243 NO_STUFF_10pF C260 NO_STUFF_10pF CR17 NO_STUFF_BAR43 1 3 R147 1K RP23C 33 3...

Page 344: ...34 H_INIT 3 34 LAN_EEP_DOUT 16 H_A20M 3 PCI_GNTA 16 19 PCI_GNTB 21 PCI_GNT4 21 PCI_GNT2 19 PCI_GNT1 19 PCI_GNT3 20 PCI_RST 6 23 28 34 42 BUF_PCI_RST 9 19 20 21 29 30 31 34 V3 3_ICHLAN 17 V1 8S_ICHHUB...

Page 345: ...34 PM_STPPCI 14 34 PM_SUS_STAT 9 29 31 34 PM_SUS_CLK 34 PM_CPUPERF 34 PM_STPCPU 14 34 36 38 PM_SLP_S4 29 34 41 LPC_FRAME 28 29 30 31 34 V_RTC 17 18 V3 3ALWAYS 5 9 17 18 19 20 24 25 26 29 33 34 36 41 V...

Page 346: ...S88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS0 VSS1 VSS2 VSS3 VSS4 VSS12 VSS5 VSS7 VSS8 VSS9 VSS10 VSS11 VSS6 VSS15 VSS14 VSS13 VSS16 VSS17 VSS18 VSS19 VSS20...

Page 347: ...H_FAB_REV2 16 V5A_PWRGD 36 V3 3S_ICH 16 17 19 21 34 V12S 9 14 20 24 34 41 V12S 9 14 20 24 34 41 V3 3S_ICH 16 17 19 21 34 V3 3ALWAYS_ICH 17 34 V3 3ALWAYS_ICH 17 34 V3 3S 5 9 10 14 15 17 20 23 28 30 31...

Page 348: ...PME 9 15 20 34 PCI_PME 9 15 20 34 PCI_REQ1 15 18 PCI_REQ2 15 18 V5_PCI 20 V5S_PCI 20 V3 3S_PCI 20 V5S_PCI 20 V3 3S_PCI 20 V12S_PCI 20 V3 3S_PCI 20 V5S_PCI 20 V3 3ALWAYS 5 9 16 17 18 20 24 25 26 29 33...

Page 349: ...1 42 V5PCISLT3 V3 3S 5 9 10 14 15 17 18 23 28 30 31 32 33 36 37 38 41 42 V12S 19 41 V5PCISLT3 V3 3ALWAYS 5 9 16 17 18 19 24 25 26 29 33 34 36 41 V3 3PCISLT3 V3 3PCISLT3 V12S_PCI 19 V5_PCI 19 V3 3S_PCI...

Page 350: ...5 18 DOCK_SMBDATA 22 DOCK_SMBCLK 22 SMB_DATA 10 14 15 18 DOCK_REQB 22 DOCK_QDEN 22 DOCK_DOCKINTR 22 DOCK_REQ4 22 DOCK_QPCIEN 22 PCI_GNTB 15 PCI_GNT4 15 CLK_DOCKPCI 14 BUF_PCI_RST 9 15 19 20 29 30 31 3...

Page 351: ...LPT_D5 LPT_D4 GND39 ERROR LPT_D1 LPT_D0 GND40 SER_OUT SER_RTS SER_CTS SER_DTR MS_DATA MS_CLK GND41 L_LININ LIN_GND R_LININ NC8 MIDI_SRX MIDI_STX USB USB GND42 DCKINTR J38B 200Pin_Docking Plug 51 52 53...

Page 352: ...DE_PDA2 16 IDE_PDCS3 16 IDE_SDA2 16 IDE_SDCS3 16 IDE_PDCS1 16 IDE_PDA0 16 IDE_PDIOR 16 IDE_PDIOW 16 IDE_PDDACK 16 IDE_SDA1 16 IDE_SDIOR 16 IDE_SDCS1 16 IDE_SDDACK 16 IDE_SDA0 16 IDE_SDIOW 16 IDE_PDA1...

Page 353: ...1 16 IDE_D_SRST 23 V5 17 18 19 20 34 40 41 V3 3 7 9 15 17 20 27 29 32 34 36 40 41 V3 3ALWAYS 5 9 16 17 18 19 20 25 26 29 33 34 36 41 V5S 9 17 20 21 31 32 33 35 36 37 38 41 42 V3 3 7 9 15 17 20 27 29 3...

Page 354: ...AYS 5 9 16 17 18 19 20 24 26 29 33 34 36 41 C39 0 1UF Clamping Diode CR29 2 1 C18 0 1UF U11 TPS2052 1 2 3 4 5 6 7 8 GND IN EN1 EN2 OC2 OUT2 OUT1 OC1 U12 TPS2052 1 2 3 4 5 6 7 8 GND IN EN1 EN2 OC2 OUT2...

Page 355: ...6 17 18 19 20 24 25 29 33 34 36 41 V3 3ALWAYS 5 9 16 17 18 19 20 24 25 29 33 34 36 41 V5_ALWAYS 17 18 25 Clamping Diode CR18 2 1 TOP PORT BOTTOM PORT J8B STACKED_RJ45_USB 1 5 4 8 2 3 6 7 VCC1 VCC2 GND...

Page 356: ...AN_TXD1 15 LAN_JCLK 15 LAN_RXD2 15 LAN_RXD0 15 LAN_RXD1 15 V3 3 7 9 15 17 20 24 29 32 34 36 40 41 V3 3_LAN V3 3_LAN V3 3_LAN C3 0 1UF L1 4 7UH 1 2 C7 4 7UF C2 0 1UF C26 4 7UF C23 0 1UF C25 0 1UF Platf...

Page 357: ...LPC_AD2 16 29 30 31 34 LPC_AD3 16 29 30 31 34 LPC_AD1 16 29 30 31 34 FWH_TBL 16 34 FWH_WP 16 34 LPC_FRAME 16 29 30 31 34 PCI_RST 6 15 23 34 42 FWH_INIT 15 CLK_FWHPCI 14 V3 3S 5 9 10 14 15 17 18 20 23...

Page 358: ...GATE 33 34 PM_BATLOW 16 33 34 SMC_WAKE_SCI 16 33 34 PCI_GATED_RST 9 19 20 34 V3 3ALWAYS_KBC 30 V3 3ALWAYS_KBC 30 V3 3 7 9 15 17 20 24 27 32 34 36 40 41 V3 3ALWAYS 5 9 16 17 18 19 20 24 25 26 33 34 36...

Page 359: ...34 SMC_INITCLK 24 29 SMC_RST 29 V3 3S 5 9 10 14 15 17 18 20 23 28 31 32 33 36 37 38 41 42 V3 3S 5 9 10 14 15 17 18 20 23 28 31 32 33 36 37 38 41 42 V3 3S 5 9 10 14 15 17 18 20 23 28 31 32 33 36 37 38...

Page 360: ...0PF 1 2 RP21A 1K 1 8 R145 33 RP20B 33 2 7 DS9 GREEN 1 2 C458 330PF 1 2 RP17C 33 3 6 R150 4 7K R185 100 C239 330PF 1 2 C236 330PF 1 2 RP21D 1K 4 5 RP20A 33 1 8 R220 0 01_1 DS12 GREEN 1 2 DS14 GREEN 1 2...

Page 361: ...1 FLP_INDEX 31 FLP_WP 31 PPT_SLCT 31 PPT_ERR 31 PPT_ACK 31 PPT_PE 31 PPT_BUSY WAIT 31 PPT_PNF 31 IR_RXD 31 SER_CTSA 31 SER_SINA 31 SER_RIA 31 SER_DSRA 31 SER_DCDA 31 V3 3S_IR V5S 9 17 20 21 24 31 33 3...

Page 362: ...0 29 KBC_A20GATE 29 34 SMB_SB_ALRT 29 34 41 DOCK_INTR 21 29 34 KBC_SCANIN 7 0 29 H_A20GATE 15 V5S 9 17 20 21 24 31 32 35 36 37 38 41 42 V3 3ALWAYS 5 9 16 17 18 19 20 24 25 26 29 34 36 41 V3 3S 5 9 10...

Page 363: ...H_CPUSLP 3 15 LPC_DRQ 0 16 31 SMC_RUNTIME_SCI 16 29 33 SMC_WAKE_SCI 16 29 33 FAN_ON 29 35 PM_BATLOW 16 29 33 FWH_TBL 16 28 FWH_WP 16 28 PM_THRM 5 16 18 29 PM_PWRBTN 16 29 VR_ON 29 37 SMC_SHUTDOWN 29...

Page 364: ...ebruary 24 2003 855PM Platform Title Size Document Number Rev Date Sheet of Project V5_FAN FAN_ON_Q FAN_ON_D FAN_ON 29 34 V5S 9 17 20 21 24 31 32 33 36 37 38 41 42 R125 1M R127 100K CR15 1N4148 1 3 CO...

Page 365: ...H_D U43_TP2 U43_TP1 VR_VID5 38 42 VR_VID4 38 42 VR_VID3 38 42 PM_DPRSLPVR 16 34 38 PM_STPCPU 14 16 34 38 TP_NC_5 3 ON_BOARD_VR_PWRGD 38 CORE_VR_ON 37 PWR_PWROK 41 V1 5_PWRGD 17 DDR_VR_PWRGD 40 VR_SHUT...

Page 366: ...d Processor IO VR s VCCP 855PM VR AND VCCP C 37 47 Monday February 24 2003 855PM Platform Title Size Document Number Rev Date Sheet of Project VCCP 3 4 5 7 15 16 17 39 V5S 9 17 20 21 24 31 32 33 35 36...

Page 367: ...Monday February 24 2003 855PM Platform Title Size Document Number Rev Date Sheet of Project PM_DPRSLPVR 16 34 36 VDC 18 36 41 V3 3S 5 9 10 14 15 17 18 20 23 28 30 31 32 33 36 41 ON_BOARD_VR_ON 36 ON_...

Page 368: ...139 150UF C122 NO_STUFF_10UF C379 2 2uF C366 NO_STUFF_10UF C371 NO_STUFF_10UF C104 150UF C393 0 1UF C422 0 1UF C117 NO_STUFF_10UF C390 2 2uF C136 150UF C381 2 2uF C171 150UF C425 0 022uF C362 NO_STUFF...

Page 369: ...C494 0 082uF R423 NO_STUFF_10K_1 VDD GND U40A TLV2463 1 3 2 4 5 10 R223 0 R476 3 92k_1 Note for layout This part has special pad on it s underside U34 TPS54610 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17...

Page 370: ...7 20 21 24 31 32 33 35 36 37 38 42 V12S 19 20 V5S 9 17 20 21 24 31 32 33 35 36 37 38 42 V5S 9 17 20 21 24 31 32 33 35 36 37 38 42 V1 5S 4 6 7 9 17 V3 3 7 9 15 17 20 24 27 29 32 34 36 40 V3 3S 5 9 10 1...

Page 371: ...A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE INTENTIONALLY LEFT BLANK DEBUG LOGIC A 42 47 Monday February 24 2003 855PM Platform Title Size Document Number Rev Date Sheet of Project...

Page 372: ...U PG 3 18 ON_BOARD_VR_PWRGD PG 37 855PM VCCP VR PG 38 VR_PWRGD_CK408 VR_PWRGD_ICH PG 36 16 17 2 5 PG 41 U52 4 PM_SLP_S4 PG 41 DC_SLP_S5 V1 5S 6 V5S 6 V12S 6 V5 6 V3 3S 6 V3 3 6 VDC 6 V12S 6 PG 38 PG 3...

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Intel 855PM, Design Manual

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