Platform Power Requirements
R
Intel
®
855PM Chipset Platform Design Guide
121
The top right side of Figure 70 shows how most of Layer 5 under the MCH package outline is a ground
plane except for a narrow corridor that allows escape of the V
CC-MCH
out of the pin field. This is possible
since Layer 5 does not need to be ground in this area since there are no signals routed on Layer 6 in this
area that needs to be ground referenced to Layer 5. However, due to the via antipads the V
CC-MCH
corridor is fairly narrow. Thus, another somewhat wider V
CC-MCH
plane flood corridor is created in
between the FSB and AGP signals for escape routing on Layer 6 as illustrated on the bottom right side
of Figure 70. Both Layer 5 and Layer 6 V
CC-MCH
floods get connected to a VR feed point.
The bottom left side of Figure 70 illustrates how the V
CC-MCH
flood on the secondary side is shorted to
the four 0603 and one 2.2 µF 0805 form factor capacitors to the V
CC-MCH
pins. As the Layer 5 and Layer
6 V
CC-MCH
floods continue to the VR feed point, they are also via’ed down with the four pairs of V
CC-MCH
and ground vias to connect the two, 150-µF POSCAPs placed on the secondary side layer (Layer 8).
Notice that the vias are placed under the body of the POSCAPs and connect to two small V
CC-MCH
and
ground floods on the secondary side that connect the vias to the POSCAP pads. This is done to
minimize the ESL of the POSCAPs in this connection.
In Figure 70 and Figure 71, placement of the POSCAPs on the secondary side is recommended since
Layer 5 and Layer 6 are much closer to the secondary side thus lower ESL will result for this
connection.
Figure 69. V
CC-MCH
Power Delivery and Decoupling Concept
ODEM SIL
ODEM SIL
PSB Side
DDR Side
2.5v
1.2v
1.05v
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
855PM Silicon Die
855PM Silicon Die
0603 and 0805 Caps
2x150uF POSCAPS
Intel 855PM MCH-M
ODEM SIL
ODEM SIL
PSB Side
DDR Side
2.5v
1.2v
1.05v
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
855PM Silicon Die
855PM Silicon Die
0603 and 0805 Caps
2x150uF POSCAPS
Intel 855PM MCH-M
Intel 855PM MCH
ODEM SIL
ODEM SIL
PSB Side
DDR Side
2.5v
1.2v
1.05v
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
855PM Silicon Die
855PM Silicon Die
0603 and 0805 Caps
2x150uF POSCAPS
Intel 855PM MCH-M
ODEM SIL
ODEM SIL
PSB Side
DDR Side
2.5v
1.2v
1.05v
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
855PM Silicon Die
855PM Silicon Die
0603 and 0805 Caps
2x150uF POSCAPS
Intel 855PM MCH-M
Intel 855PM MCH
Figure 70 illustrates how the conceptual cross section of the V
CC-MCH
power delivery in Figure 69
translates into an actual recommended layout as implemented on the primary side layer (Layer 1), Layer
4, Layer 5, and secondary side layer (Layer 8). The top left side of Figure 70 shows how the BGA balls
and the vias are shorted with a small V
CC-MCH
plane flood on the primary side. Notice the orientation of
the dog bones since this is critical to fit all the required components on the secondary side.
The top right side of Figure 70 shows how most of Layer 5 under the Intel 855PM MCH package
outline shadow is a ground plane except for a narrow corridor that allows for the escape routing of the
V
CC-MCH
out of the pin field. This is possible since Layer 5 does not need to be ground in this area since
there are no signals routed on Layer 6 in this area that needs to use Layer 5 for ground referencing.
However, due to the via antipads, the V
CC-MCH
corridor is fairly narrow. Thus, another somewhat wider
V
CC-MCH
plane flood corridor is created in between the FSB and AGP signals for escape routing on
Layer 6 as illustrated in bottom right side of Figure 70. Both Layer 5 and Layer 6 V
CC-MCH
floods get
connected to a VR feed point.
The bottom left side of Figure 70 illustrates the V
CC-MCH
flood on the secondary side shorted to the five,
0603 form factor capacitors and one, 2.2-µF 0805 form factor capacitor to the V
CC-MCH
pins. As the
