FSB Design Guidelines
R
74
Intel
®
855PM Chipset Platform Design Guide
Table 16. ITP Signal Default Strapping When ITP Debug Port Not Used
Signal
Resistor Value
Connect To
Resistor Placement
TDI
150
±
5%
V
CCP
Within 2.0” of the CPU
TMS
39
±
5%
V
CCP
Within 2.0” of the CPU
TRST#
680
±
5%
GND
Within 2.0” of the CPU
TCK
27
±
5%
GND
Within 2.0” of the CPU
TDO Open NC
N/A
Figure 39 illustrates the recommended layout for the processor’s strapping resistors. To avoid
interaction with FSB routing, the TEST[3:1] signal resistors are placed on the secondary side of the
motherboard. To avoid GND via interaction with the FSB routing, the resistors share GND via
connections with the A8, A17, and A20 ground pins of the processor.
The 150-
pull-up resistor to V
CCP
(1.05 V) for TDI is shown in Figure 39 on the secondary side of the
board. The placement of the strapping resistors for TDI, TMS, TRST#, and TCK is not critical.
Figure 39. Processor Strapping Resistor Layout
SECONDARY SIDE
TEST[2]
TEST[1]
A8, A17 & A20
GND
Pins
TEST[3]
TDI
TMS
TRST#
TCK
