FSB Design Guidelines
R
82
Intel
®
855PM Chipset Platform Design Guide
Table 17. Recommended ITP700FLEX Signal Terminations
Signal
Termination Value
Termination Voltage Termination/Decap
Location Notes
TDI
150
±
5%
V
CCP
(1.05 V)
Within
±
300 ps of the processor
TDI pin
5
TMS
39.2
±
1%
V
CCP
(1.05 V)
Within
±
200 ps of the ITP700FLEX
connector TMS pin
5
TRST#
510 – 680
±
5%
GND
Anywhere between processor and
ITP700FLEX connector
5
TCK
27.4
±
1%
GND
Within
±
200 ps of the ITP700
FLEX connector TCK pin
5
TDO
54.9
±
1% pull-up and
22.6
±
1% series
resistor
V
CCP
(1.05 V)
Within 1” of the ITP700FLEX
connector TDO pin
1, 5
BCLK(p/n)
2
FBO
Connect to TCK pin of
CPU
N/A N/A
1
RESET#
54.9
±
1% pull-up and
22.6
±
1% series
resistor
V
CCP
(1.05 V)
Within 0.5” of the ITP700FLEX
connector RESET# pin
1
BPM[5:0]# Not
Required
3
DBA#
150-240
±
5%
VCC of target system
recovery circuit.
Within 1 ns of the ITP700FLEX
connector DBA# pin
4
DBR#
150-240
±
5%
VCC of target system
recovery circuit
Within 1 ns of the ITP700FLEX
connector DBR# pin
VTAP
Short to
V
CCP
plane
V
CCP
(1.05 V)
VTT
Short to
V
CCP
plane
V
CCP
(1.05 V)
Add 0.1-µF decap within 0.1 inch of
VTT pins of ITP700FLEX connector
NOTES:
1.
See Figure 41.
2.
Refer to Section 4.3.1.1.
3.
All the needed terminations to guarantee proper signal quality are integrated inside the processor AGTL+ buffers
or inside the ITP700FLEX debug port. No need for any external components for the BPM[5:0]# signals.
4.
Only required if DBA# is used with any target system circuitry. This signal may be left unconnected if unused.
5.
In cases where a system is designed to utilize the ITP700FLEX debug port for debug purposes but the
ITP700FLEX connector may or may not be populated at all times although the signal routing and termination or
decoupling components are implemented, the component placement guidelines should adhere to the ones listed
in Table 17. However, for signals where the termination component placement guidelines for non-ITP700FLEX
supported systems (see Table 16) are more restrictive or conservative than the component placement guidelines
for the ITP700FLEX supported case, then the more conservative/restrictive guidelines should be followed.
4.3.1.2.
ITP Signal Routing Example
Figure 43 illustrates a recommended layout example for the ITP700FLEX signals. The ITP700FLEX
connector is placed on the primary side of the motherboard and results in a smooth, straight-forward
routing solution.
Note that the V
CCP
(1.05 V) power delivery continues from the processor socket cavity on the secondary
side of the motherboard through the pin field as shown on the right side of Figure 43. Three V
CCP
vias in
conjunction with three ground stitching vias allow a transition to the primary side to connect to the VTT
and VTAP pins of the ITP700FLEX connector and also a transition back to the secondary side of the
