General Design Considerations
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Intel
®
855PM Chipset Platform Design Guide
31
4.
All high-speed signals should reference solid ground planes through the length of their routing
and should not cross plane splits. To guarantee this, both planes surrounding strip-lines should be
GND.
5.
Intel recommends that high-speed signal routing be done on internal, strip-line layers.
6.
High-speed signals transitioning between layers next to the component, signal pins should be
accounted for by the GND stitching vias that would stitch all the GND plane layers in that area of
the motherboard. Due to the arrangement of the Intel® Pentium® M Processor / Intel® Celeron®
M Processor and Intel 855PM MCH pin-maps, GND vias placed near all GND lands will also be
very close to high-speed signals that may be transitioning to an internal layer. Thus, no additional
ground stitching vias (besides the GND pin vias) are required in the immediate vicinity of the
processor and MCH packages to accompany the signal transitions from the component side into
an internal layer.
7.
High-speed routing on external layers should be minimized in order to avoid EMI. Routing on
external layers also introduces different delays compared to internal layers, making it extremely
difficult to do length matching if some routing is done on both internal and external layers.
