TC1784
Analog to Digital Converter (ADC)
User´s Manual
23-16
V1.1, 2011-05
ADC, V1.3
23.2.1
Register Overview
shows all registers required for programming the ADC module. It
summarizes the ADC kernel registers and defines their relative addresses and the reset
values. The relative addresses have to be added to the base addresses for the ADC
kernels (see
) to obtain the absolute address for each register. Each ADC
kernel is located in an address window of 4 * 256 bytes.
All registers can be accessed with 8 bit, 16 bit, or 32 bit wide accesses.
The prefix “
ADCx_
” has to be added to the register names in this table for each ADC
kernel to distinguish registers of the different kernels. In this naming convention, x
indicates the kernel number (e.g. ADC0_ for the ADC0 kernel and “ADC1_” for the ADC1
kernel).
The registers that are implemented only once in the ADC module are located in the
address range of ADC0.
All ADC registers (including KSCFG.NOMCFG and KSCFG.COMCFG) are reset by an
application reset (class 3), whereas bit field KSCFG.SUMCFG is reset by a debug reset
(class 1).
Note: Register bits marked “w” always deliver 0 when read.
Access rights within the address range of an ADC kernel:
•
Read or write access to defined register addresses: U, SV
•
Accesses to empty addresses: reserved, BE
Table 23-2
Register Overview of ADC
Short
Name
Description
Offset
Addr.
1)
Access Mode Reset
Description
See
Read
Write
ADC Module Registers (only available in the address range of ADC0)
CLC
Clock Control Register
000
H
U, SV SV, E Class 3
KSCFG
Kernel State
Configuration Register
00C
H
U, SV SV, E Class 3
SRCx
x = 0 - 5
Service Request Control
Registers
3FC
H
-
x * 4
H
U, SV U, SV Class 3
General Kernel Registers (available in the address range of each kernel)
ID
Module Identification
Register
008
H
U, SV U, SV Class 3
RSIRx
(x = 0 - 4)
Request Source x Input
Register
010
H
+
x * 4
U, SV U, SV Class 3
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