Infineon Technologies TC1784, Руководство пользователя

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-241 V1.1, 2011-05
GPTA
®
v5, V1.14
3. Write sequentially the multiplexer control register contents one after the other
(24 values) into MRADIN, starting with the register values for OMCRH10, OMCRL10,
… up to LIMCRH0, LIMCRL0 (see
Figure 21-90 ). After the first MRADIN write
operation, the contents for OMCRH10 is at FIFO position 1. With each following
MRADIN write operation, it becomes shifted one FIFO position upwards. After the 24.
MRADIN write operation, the OMCRH10 value is at its final position. The contents of
FIFO position 24 can be read via register MRADOUT. With each MRADIN write
operation the write cycle counter MRACTL.FIFOFILLCNT is incremented by 1. After
all FIFO entries have been written, the FIFO is locked, bit MRACTL.FIFOFULL is set,
and further MRADIN write operations are discarded until bit MRACTL.WCRES is
written again with a 0.
4. Enable the multiplexer array by writing MRACTL.MAEN = 1. This establishes and
enables all programmed interconnections.
To check the FIFO contents, the FIFO can be written a second time. At this check
MRADIN is written before MRADOUT is read. This will return the FIFO contents of the
first write sequence in the order of OMCRH10, OMCRL10, …, LIMCRL0.
Before disabling the multiplexer array FIFO, LTCA output pins that are already enabled
as LTCA output should be switched to GPIO function to avoid output spikes. After
enabling the multiplexer array FIFO again, the LTCA output can be switched again back
to LTCA output function.
Shifting the write data through the FIFO requires a few clock cycles. When new data
becomes written before the FIFO is ready to accept them, wait states will be inserted into
the write access.
If the OMCRLg register bit field OMGn of the multiplexer array is programmed with an
invalid (reserved) value, the related outputs will be forced to 0. When the array is
disabled (MRACTL.MAEN = 0), all cell inputs and outputs are disconnected from the
GPIO lines and are driven with 0.