Infineon Technologies TC1784, Руководство пользователя

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-120 V1.1, 2011-05
DMA, V3.03
11.4.3 Implementation-specific DMA Registers
The DMA controller as implemented in the TC1784 contains the following additional
registers:
•
DMA clock control register
• Service request control registers for DMA controller interrupts (DMA_SRCx)
• Service request control registers for MLI module interrupts (DMA_MLI0ySRC.x)
Figure 11-29 provides an overview of these registers.
Figure 11-29 DMA Implementation-specific Registers
Note: Further details on interrupt handling and processing are described in the “Interrupt
System” chapter of the TC1784 System Units User´s Manual.
The clock generation and interrupt control configuration as implemented in the DMA
controller module is shown in
Figure 11-29 .
The DMA controller, the Cerberus and the MLI module (MLI0) are supplied from a
common module clock
f
DMA
that has the frequency of the system clock
f
FPI
and is
controlled via the DMA_CLC clock control register. The MLI module nor the Cerberus
module does not have its own clock control register. Their input clock is derived from the
DMA clock divided by separate fractional divider registers.
The control of the suspend and break features is done independently inside each
module.
DMA Interrupt
Registers
Control Register
DMA_CLC DMA_SRC0
DMA_SRC1
DMA_SRC2
DMA_SRC3
MCA06177a
MLI Interrupt
Registers
DMA_MLI0SRC0
DMA_MLI0SRC1
DMA_MLI0SRC2
DMA_MLI0SRC3
DMA_SRC4
DMA_SRC5
DMA_SRC6
DMA_SRC7