Infineon Technologies TC1784, Руководство пользователя

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-35 V1.1, 2011-05
GPTA
®
v5, V1.14
implemented to compensate for the lack of generated output pulses:
The length of the current input signal period has been overestimated by a certain
number of
f
GPTA
clock periods. This deficit should be subtracted from the calculated
length of the next input signal period.
The PLL can continue to operate with the old input signal period length estimation,
but the number of output pulses to be generated during the next input clock period
may be increased by the lack of output pulses initiated during the last signal period.
Figure 21-23 Compensation of Input Signal Acceleration
Additionally to the normal output signal, the PLL provides an uncompensated output
signal. This signal has no gaps or acceleration bursts. However, the number of
microticks during one signal period may be incorrect.
21.3.2.5 Clock Distribution Cell (CDC)
The Clock Distribution Cells (CDC) provides all Local and Global Timer Cells with a clock
bus containing eight different clock output signals CLK[7:0] and a special LTC prescaler
clock LTCPRE. These nine clock signals are generated out of eleven clock input signals
coming from different clock sources (see
Figure 21-24 ).
The prescalers divide the GPTA
®
v5 module clock
f
GPTA
by a programmable 2
n
factor.
Factor n is defined by bit fields DFA02, DFA04, DFA06 and DFA07 of control register
MCT05932_mod
Signal Output
AEN = 0
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5
0 1 2 3 4 5 6 7 8 9 A B CDEF 0 1
Microtick Counter
AEN = 0
Time
Time
Signal_Output
AEN, PEN = 1
Microtick Counter
AEN, PEN = 1
Accelerated
Input Signal
Steady State
Input Signal